a40435af84
For Exynos/snow, cpu_info and power modules and also some parts of the GPIO API (which require timer and pwm modules) are not used in the current bootblock. Clock init only needs to be used if early console is enabled. Now our bootblock is 22420 bytes with early serial console and 11192 bytes without. Those include the 8KB BL1 region. Change-Id: I9c958dafb9cf522df0dcfbef373ce741aa162544 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2322 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
37 lines
1.2 KiB
Makefile
37 lines
1.2 KiB
Makefile
# Run an intermediate step when producing coreboot.rom
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# that adds additional components to the final firmware
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# image outside of CBFS
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#INTERMEDIATE += exynos5250_add_bl1
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bootblock-y += pinmux.c
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# Clock is required for UART
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bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c
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bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c
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bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c
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bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c
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romstage-y += clock.c
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romstage-y += clock_init.c
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romstage-y += pinmux.c # required by s3c24x0_i2c (s5p-common) and uart.
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romstage-y += exynos_cache.c
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romstage-y += dmc_common.c
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romstage-y += dmc_init_ddr3.c
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romstage-$(CONFIG_EARLY_CONSOLE) += soc.c
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romstage-$(CONFIG_EARLY_CONSOLE) += uart.c
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#ramstage-y += tzpc_init.c
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ramstage-y += clock.c
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ramstage-y += clock_init.c
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ramstage-y += exynos_cache.c
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ramstage-y += pinmux.c
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ramstage-y += power.c
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ramstage-y += soc.c
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ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
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#ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c
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#ramstage-$(CONFIG_SATA_AHCI) += sata.c
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exynos5250_add_bl1: $(obj)/coreboot.pre
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printf " DD Adding Samsung Exynos5250 BL1\n"
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dd if=3rdparty/cpu/samsung/exynos5250/E5250.nbl1.bin \
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of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
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