5fed693a52
Each HART of a SoC like fu540 supports a different ISA. In order for the coreboot's code can run on each core, need to modify the compile options. So add this code. Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
38 lines
919 B
Text
38 lines
919 B
Text
# This file is part of the coreboot project.
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#
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# Copyright (C) 2018 Jonathan Neuschäfer
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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config SOC_SIFIVE_FU540
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bool
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select ARCH_RISCV
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select ARCH_BOOTBLOCK_RISCV
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select ARCH_VERSTAGE_RISCV
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select ARCH_ROMSTAGE_RISCV
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select ARCH_RAMSTAGE_RISCV
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select BOOTBLOCK_CONSOLE
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select DRIVERS_UART_SIFIVE
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if SOC_SIFIVE_FU540
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config RISCV_ARCH
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string
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default "rv64imac"
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config RISCV_ABI
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string
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default "lp64"
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config RISCV_CODEMODEL
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string
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default "medany"
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endif
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