f0d21ff3da
This patch aligns tegra124 to the new SoC header include scheme. Also alphabetized headers in affected files since we touch them anyway. BUG=None TEST=Tested with whole series. Compiled Nyan, Nyan_Big and Nyan_Blaze. Change-Id: Ia82ab86b2af903690cc6c9d310f7bdda3425ea7c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d23774e071ec22781991ff20fbf63802f620c88 Original-Change-Id: Ia126cff8590117788d1872e50608c257d2659c1f Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/224504 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9326 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <boardid.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/i2c.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <reset.h>
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#include "pmic.h"
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enum {
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AS3722_I2C_ADDR = 0x40
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};
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struct as3722_init_reg {
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u8 reg;
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u8 val;
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u8 delay;
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};
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static struct as3722_init_reg init_list[] = {
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{AS3722_SDO0, 0x3C, 1},
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{AS3722_SDO1, 0x32, 0},
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{AS3722_LDO3, 0x59, 0},
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{AS3722_SDO2, 0x3C, 0},
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{AS3722_SDO3, 0x00, 0},
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{AS3722_SDO4, 0x00, 0},
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{AS3722_SDO5, 0x50, 0},
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{AS3722_SDO6, 0x28, 1},
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{AS3722_LDO0, 0x8A, 0},
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{AS3722_LDO1, 0x00, 0},
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{AS3722_LDO2, 0x10, 0},
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{AS3722_LDO4, 0x00, 0},
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{AS3722_LDO5, 0x00, 0},
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{AS3722_LDO6, 0x00, 0},
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{AS3722_LDO7, 0x00, 0},
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{AS3722_LDO9, 0x00, 0},
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{AS3722_LDO10, 0x00, 0},
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{AS3722_LDO11, 0x00, 1},
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};
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static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
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{
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if (i2c_writeb(bus, AS3722_I2C_ADDR, reg, val)) {
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printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
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__func__, reg, val);
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/* Reset the SoC on any PMIC write error */
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hard_reset();
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} else {
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if (do_delay)
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udelay(500);
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}
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}
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static void pmic_slam_defaults(unsigned bus)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(init_list); i++) {
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struct as3722_init_reg *reg = &init_list[i];
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pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
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}
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}
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void pmic_init(unsigned bus)
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{
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/*
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* Don't need to set up VDD_CORE - already done - by OTP
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* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
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* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
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*/
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/* Restore PMIC POR defaults, in case kernel changed 'em */
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pmic_slam_defaults(bus);
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/* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
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pmic_write_reg(bus, 0x00, 0x50, 1);
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/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
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pmic_write_reg(bus, 0x06, 0x28, 1);
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/*
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* First set +1.2V_GEN_AVDD to 1.2V, then enable the +1.2V_GEN_AVDD
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* regulator.
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*/
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pmic_write_reg(bus, 0x12, 0x10, 1);
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/*
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* Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
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* the value (register 0x20 bit 4)
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*/
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pmic_write_reg(bus, 0x0c, 0x07, 0);
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pmic_write_reg(bus, 0x20, 0x10, 1);
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}
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