Rob Barnes 4454c9af3c soc/amd/cezanne: Correct S0i3 verstage softfuse bit ... PSP_S0I3_RESUME_VERSTAGE softfuse bit is 58, not 40. BUG=b:202397678 BRANCH=None TEST=Boot guybrush, ensure S0i3 verstage runs with latest PSP. Change-Id: Ia27f6e48e345aac0d5f6579d663a6b655688239a Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>		2021-12-20 17:52:50 +00:00
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cezanne	soc/amd/cezanne: Correct S0i3 verstage softfuse bit	2021-12-20 17:52:50 +00:00
common	soc/amd/common/lpc/espi_util: use enum cb_err type for return values	2021-12-20 17:40:52 +00:00
picasso	soc/amd: remove root of SoC directory from include path	2021-12-20 09:51:49 +00:00
stoneyridge	soc/amd/stoneyridge/fch: add GNVS-related TODOs	2021-12-20 17:38:54 +00:00
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