09f2921b5d
This patch ports the LZ4 decompression code that debuted in libpayload last year to coreboot for use in CBFS stages (upgrading the base algorithm to LZ4's dev branch to access the new in-place decompression checks). This is especially useful for pre-RAM stages in constrained SRAM-based systems, which previously could not be compressed due to the size requirements of the LZMA scratchpad and bounce buffer. The LZ4 algorithm offers a very lean decompressor function and in-place decompression support to achieve roughly the same boot speed gains (trading compression ratio for decompression time) with nearly no memory overhead. For now we only activate it for the stages that had previously not been compressed at all on non-XIP (read: non-x86) boards. In the future we may also consider replacing LZMA completely for certain boards, since which algorithm wins out on boot speed depends on board-specific parameters (architecture, processor speed, SPI transfer rate, etc.). BRANCH=None BUG=None TEST=Built and booted Oak, Jerry, Nyan and Falco. Measured boot time on Oak to be about ~20ms faster (cutting load times for affected stages almost in half). Change-Id: Iec256c0e6d585d1b69985461939884a54e3ab900 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13638 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
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| .. | ||
| accessors | ||
| cli | ||
| COPYING | ||
| ChangeLog | ||
| DISCLAIMER | ||
| Makefile | ||
| Makefile.inc | ||
| README | ||
| cbfs.c | ||
| cbfs.h | ||
| cmos_lowlevel.c | ||
| cmos_lowlevel.h | ||
| cmos_ops.c | ||
| cmos_ops.h | ||
| common.c | ||
| common.h | ||
| compute_ip_checksum.c | ||
| coreboot_tables.h | ||
| hexdump.c | ||
| hexdump.h | ||
| input_file.c | ||
| input_file.h | ||
| ip_checksum.h | ||
| layout.c | ||
| layout.h | ||
| lbtable.c | ||
| lbtable.h | ||
| nvramtool.spec | ||
| reg_expr.c | ||
| reg_expr.h | ||
| win32mmap.c | ||
README
Summary of Operation
--------------------
nvramtool is a utility for reading/writing coreboot parameters and
displaying information from the coreboot table. It is intended for x86-based
systems (both 32-bit and 64-bit) that use coreboot.
The coreboot table resides in low physical memory, and may be accessed
through the /dev/mem interface. It is created at boot time by coreboot, and
contains various system information such as the type of mainboard in use. It
specifies locations in the CMOS (nonvolatile RAM) where the coreboot
parameters are stored.
For information about coreboot, see http://www.coreboot.org/.
Ideas for Future Improvements
-----------------------------
1. Move the core functionality of this program into a shared library.
2. Consider adding options for displaying other BIOS-provided information
such as the MP table, ACPI table, PCI IRQ routing table, etc.