a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
69 lines
2.4 KiB
C
69 lines
2.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Written by Stefan Reinauer <stepan@openbios.org>
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* (C) 2005 Stefan Reinauer
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* (C) 2005 Digital Design Corporation
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*
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* Ported to Intel XE7501DEVKIT by Agami Aruma
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* Ported to AOpen DXPL Plus-U by Kyösti Mälkki
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <string.h>
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#include <arch/acpi.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <assert.h>
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#include "bus.h"
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unsigned long acpi_fill_madt(unsigned long current)
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{
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unsigned int irq_start = 0;
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device_t dev = 0;
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struct resource* res = NULL;
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// SJM: Hard-code CPU LAPIC entries for now
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current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
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current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6);
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current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1);
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current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7);
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// Southbridge IOAPIC
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, 0xfec00000, irq_start);
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irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
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// P64H2 Bus B IOAPIC
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dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
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if (!dev)
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BUG(); // Config.lb error?
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start);
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irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
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// P64H2 Bus A IOAPIC
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dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
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if (!dev)
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BUG(); // Config.lb error?
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res = find_resource(dev, PCI_BASE_ADDRESS_0);
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current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start);
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irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
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// Map ISA IRQ 0 to IRQ 2
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
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// IRQ9 differs from ISA standard - ours is active high, level-triggered
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current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
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return current;
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}
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