a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
128 lines
3.2 KiB
C
128 lines
3.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <console/console.h>
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#include <arch/io.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/smm.h>
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#include <string.h>
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#include <soc/iomap.h>
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#include <soc/pmc.h>
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#include <soc/smm.h>
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/* Save settings which will be committed in SMI functions. */
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static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT];
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void southcluster_smm_save_param(int param, uint32_t data)
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{
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smm_save_params[param] = data;
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}
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void southcluster_smm_clear_state(void)
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{
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uint32_t smi_en;
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/* Log events from chipset before clearing */
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southcluster_log_state();
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printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
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printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase());
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smi_en = inl(get_pmbase() + SMI_EN);
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if (smi_en & APMC_EN) {
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printk(BIOS_INFO, "SMI# handler already enabled?\n");
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return;
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}
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/* Dump and clear status registers */
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clear_smi_status();
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clear_pm1_status();
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clear_tco_status();
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clear_gpe_status();
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clear_alt_status();
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clear_pmc_status();
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}
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static void southcluster_smm_route_gpios(void)
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{
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u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
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const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
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uint32_t alt_gpio_reg = 0;
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uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE];
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int i;
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printk(BIOS_DEBUG, "GPIO_ROUT = %08x\n", route_reg);
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/* Start the routing for the specific gpios. */
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write32(gpio_rout, route_reg);
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/* Enable SMIs for the gpios that are set to trigger the SMI. */
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for (i = 0; i < 16; i++) {
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if ((route_reg & ROUTE_MASK) == ROUTE_SMI) {
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alt_gpio_reg |= (1 << i);
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}
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route_reg >>= 2;
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}
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printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg);
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outl(alt_gpio_reg, alt_gpio_smi);
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}
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void southcluster_smm_enable_smi(void)
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{
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uint16_t pm1_events = PWRBTN_EN | GBL_EN;
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printk(BIOS_DEBUG, "Enabling SMIs.\n");
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if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE])
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pm1_events |= PCIEXPWAK_DIS;
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enable_pm1(pm1_events);
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disable_gpe(PME_B0_EN);
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/* Set up the GPIO route. */
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southcluster_smm_route_gpios();
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/* Enable SMI generation:
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* - on APMC writes (io 0xb2)
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* - on writes to SLP_EN (sleep states)
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* - on writes to GBL_RLS (bios commands)
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* No SMIs:
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* - on TCO events
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* - on microcontroller writes (io 0x62/0x66)
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*/
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enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
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}
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void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
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{
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/*
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* Issue SMI to set the gnvs pointer in SMM.
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* tcg and smi1 are unused.
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*
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* EAX = APM_CNT_GNVS_UPDATE
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* EBX = gnvs pointer
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* EDX = APM_CNT
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*/
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asm volatile (
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"outb %%al, %%dx\n\t"
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: /* ignore result */
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: "a" (APM_CNT_GNVS_UPDATE),
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"b" ((uint32_t)gnvs),
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"d" (APM_CNT)
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);
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}
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