6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
148 lines
3.8 KiB
C
148 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef _PCI_MMIO_CFG_H
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#define _PCI_MMIO_CFG_H
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#include <stdint.h>
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#include <device/mmio.h>
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#include <device/pci_type.h>
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/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we
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* prevent some sub-optimal constant folding. */
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extern u8 *const pci_mmconf;
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/* Using a unique datatype for MMIO writes makes the pointers to _not_
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* qualify for pointer aliasing with any other objects in memory.
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*
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* MMIO offset is a value originally derived from 'struct device *'
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* in ramstage. For the compiler to not discard this MMIO offset value
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* from CPU registers after any MMIO writes, -fstrict-aliasing has to
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* be also set for the build.
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*
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* Bottom 12 bits (4 KiB) are reserved to address the registers of a
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* single PCI function. Declare the bank as a union to avoid some casting
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* in the functions below.
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*/
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union pci_bank {
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uint8_t reg8[4096];
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uint16_t reg16[4096 / sizeof(uint16_t)];
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uint32_t reg32[4096 / sizeof(uint32_t)];
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};
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static __always_inline
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volatile union pci_bank *pcicfg(pci_devfn_t dev)
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{
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return (void *)&pci_mmconf[PCI_DEVFN_OFFSET(dev)];
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}
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static __always_inline
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uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg)
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{
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return pcicfg(dev)->reg8[reg];
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}
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static __always_inline
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uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg)
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{
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return pcicfg(dev)->reg16[reg / sizeof(uint16_t)];
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}
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static __always_inline
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uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg)
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{
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return pcicfg(dev)->reg32[reg / sizeof(uint32_t)];
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}
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static __always_inline
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void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
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{
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pcicfg(dev)->reg8[reg] = value;
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}
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static __always_inline
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void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
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{
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pcicfg(dev)->reg16[reg / sizeof(uint16_t)] = value;
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}
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static __always_inline
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void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
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{
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pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value;
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}
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/*
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* The functions pci_mmio_config*_addr provide a way to determine the MMIO address of a PCI
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* config register. The address returned is dependent of both the MMCONF base address and the
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* assigned PCI bus number of the requested device, which both can change during the boot
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* process. Thus, the pointer returned here must not be cached!
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*/
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static __always_inline
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uint8_t *pci_mmio_config8_addr(pci_devfn_t dev, uint16_t reg)
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{
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return (uint8_t *)&pcicfg(dev)->reg8[reg];
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}
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static __always_inline
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uint16_t *pci_mmio_config16_addr(pci_devfn_t dev, uint16_t reg)
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{
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return (uint16_t *)&pcicfg(dev)->reg16[reg / sizeof(uint16_t)];
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}
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static __always_inline
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uint32_t *pci_mmio_config32_addr(pci_devfn_t dev, uint16_t reg)
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{
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return (uint32_t *)&pcicfg(dev)->reg32[reg / sizeof(uint32_t)];
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}
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#if CONFIG(MMCONF_SUPPORT)
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#if CONFIG_MMCONF_BASE_ADDRESS == 0
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#error "CONFIG_MMCONF_BASE_ADDRESS undefined!"
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#endif
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/* Avoid name collisions as different stages have different signature
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* for these functions. The _s_ stands for simple, fundamental IO or
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* MMIO variant.
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*/
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static __always_inline
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uint8_t pci_s_read_config8(pci_devfn_t dev, uint16_t reg)
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{
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return pci_mmio_read_config8(dev, reg);
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}
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static __always_inline
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uint16_t pci_s_read_config16(pci_devfn_t dev, uint16_t reg)
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{
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return pci_mmio_read_config16(dev, reg);
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}
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static __always_inline
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uint32_t pci_s_read_config32(pci_devfn_t dev, uint16_t reg)
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{
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return pci_mmio_read_config32(dev, reg);
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}
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static __always_inline
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void pci_s_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value)
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{
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pci_mmio_write_config8(dev, reg, value);
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}
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static __always_inline
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void pci_s_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value)
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{
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pci_mmio_write_config16(dev, reg, value);
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}
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static __always_inline
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void pci_s_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
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{
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pci_mmio_write_config32(dev, reg, value);
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}
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#endif
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#endif /* _PCI_MMIO_CFG_H */
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