935dff53b6
Change-Id: I92c654d59f1642bcd7c95de80dcc641bf816b542 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
39 lines
1.2 KiB
C
39 lines
1.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* The sole purpose of this driver is to avoid BAR to be changed during
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* resource allocation. Since configuration space is just 32 bytes it
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* shouldn't cause any fragmentation.
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <intelblocks/uart.h>
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#include <soc/pci_devs.h>
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void pch_uart_read_resources(struct device *dev)
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{
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pci_dev_read_resources(dev);
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if ((IS_ENABLED(CONFIG_SOC_UART_DEBUG) &&
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dev->path.pci.devfn == _PCH_DEVFN(UART,
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CONFIG_UART_FOR_CONSOLE))) {
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/* will override existing resource. */
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fixed_mem_resource(dev, PCI_BASE_ADDRESS_0,
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CONFIG_CONSOLE_UART_BASE_ADDRESS >> 10, 4, 0);
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}
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}
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