a87fcabd2e
Migrate google/ninja (AOpen Chromebox Commerical) from Chromium tree to upstream, using google/rambi as a reference. original source: branch firmware-ninja-5216.383.B commit 582a393 [Ninja, Sumo: Add SPD source for Hynix H5TC4G63CFR-PBA] TEST=built and booted Linux on ninja with full functionality blobs required for working image: VGA BIOS (vgabios.bin) firmware descriptor (ifd.bin) Intel ME firmware (me.bin) MRC (mrc.elf) external reference code (refcode.elf) Change-Id: I0f1892c24c08fa2d53185b2cf8b6f5a9001b2397 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/14950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
102 lines
3.1 KiB
Text
102 lines
3.1 KiB
Text
chip soc/intel/baytrail
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# SATA port enable mask (2 ports)
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register "sata_port_map" = "0x1"
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register "sata_ahci" = "0x1"
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register "ide_legacy_combined" = "0x0"
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# Route USB ports to XHCI
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register "usb_route_to_xhci" = "1"
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# USB Port Disable Mask
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register "usb2_port_disable_mask" = "0x0"
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register "usb3_port_disable_mask" = "0x0"
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# USB PHY settings
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# TODO: These values are from Baytrail and need tuned for Ninja board
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register "usb2_per_port_lane0" = "0x00049a09"
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register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
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register "usb2_per_port_lane1" = "0x00049a09"
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register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
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register "usb2_per_port_lane2" = "0x00049209"
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register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
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register "usb2_per_port_lane3" = "0x00049a09"
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register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
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register "usb2_comp_bg" = "0x4700"
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# LPE audio codec settings
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register "lpe_codec_clk_freq" = "25" # 25MHz clock
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register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
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# SD Card controller
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register "sdcard_cap_low" = "0x036864b2"
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register "sdcard_cap_high" = "0x0"
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# Enable devices in ACPI mode
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register "lpe_acpi_mode" = "1"
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register "lpss_acpi_mode" = "1"
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register "scc_acpi_mode" = "1"
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# Allow PCIe devices to wake system from suspend
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register "pcie_wake_enable" = "1"
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# Enable PIPEA as DP_C
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register "gpu_pipea_port_select" = "2" # DP_C
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register "gpu_pipea_power_cycle_delay" = "6" # 600ms
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register "gpu_pipea_power_on_delay" = "5000" # 500ms
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register "gpu_pipea_light_on_delay" = "70" # 7ms
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register "gpu_pipea_power_off_delay" = "500" # 50ms
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register "gpu_pipea_light_off_delay" = "2000" # 200ms
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# VR PS2 control
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register "vnn_ps2_enable" = "1"
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register "vcc_ps2_enable" = "1"
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# Disable SLP_X stretching after SUS power well fail.
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register "disable_slp_x_stretch_sus_fail" = "1"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # SoC router
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device pci 02.0 on end # GFX
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device pci 11.0 off end # SDIO
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device pci 12.0 on end # SD
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device pci 13.0 on end # SATA
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device pci 14.0 on end # XHCI
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device pci 15.0 on end # LPE
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device pci 17.0 on end # MMC
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device pci 18.0 on end # SIO_DMA1
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device pci 18.1 on end # I2C1
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device pci 18.2 on end # I2C2
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device pci 18.3 off end # I2C3
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device pci 18.4 off end # I2C4
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device pci 18.5 off end # I2C5
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device pci 18.6 off end # I2C6
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device pci 18.7 off end # I2C7
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device pci 1a.0 on end # TXE
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device pci 1b.0 on end # HDA
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device pci 1c.0 on end # PCIE_PORT1
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device pci 1c.1 off end # PCIE_PORT2
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device pci 1c.2 on end # PCIE_PORT3
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device pci 1c.3 on end # PCIE_PORT4
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device pci 1d.0 on end # EHCI
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device pci 1e.0 on end # SIO_DMA2
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device pci 1e.1 off end # PWM1
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device pci 1e.2 off end # PWM2
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device pci 1e.3 off end # HSUART1
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device pci 1e.4 off end # HSUART2
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device pci 1e.5 off end # SPI
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device pci 1f.0 on
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chip ec/google/chromeec
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# We only have one init function that
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# we need to call to initialize the
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# keyboard part of the EC.
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device pnp ff.1 on # dummy address
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end
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end
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end # LPC Bridge
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device pci 1f.3 off end # SMBus
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end
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end
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