1f86434227
This patch updates the libpayload XHCI stack to run on ARM CPUs (tested with the DWC3 controller on an Exynos5420). Firstly, it adds support for 64-byte Slot/Endpoint Context sizes. Since the existing context handling code represented the whole device context as a C struct (whose size has to be known at compile time), it was necessary to refactor the input and device context structures to consist of pointers to the actual contexts instead. Secondly, it moves all data structures that the xHC accesses through DMA to cache-coherent memory. With a similar rationale as in the ARM patches for EHCI, using explicit cache maintenance functions to correctly handle the actual transfer buffers in all cases is presumably impossible. Instead this patch also chooses to create a DMA bounce buffer in the XHCI stack where transfer buffers which are not already cache-coherent will be copied to/from. Change-Id: I14e82fffb43b4d52d687b65415f2e33920e088de Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169453 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 1fa9964063cce6cbd87ba68334806dde8aa2354c) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6643 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
136 lines
4 KiB
C
136 lines
4 KiB
C
/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2013 secunet Security Networks AG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <inttypes.h>
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#include "xhci_private.h"
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#ifdef XHCI_DUMPS
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void
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xhci_dump_slotctx(const slotctx_t *const sc)
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{
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xhci_debug("Slot Context (@%p):\n", sc);
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usb_debug(" FIELD1\t0x%08"PRIx32"\n", sc->f1);
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usb_debug(" FIELD2\t0x%08"PRIx32"\n", sc->f2);
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usb_debug(" FIELD3\t0x%08"PRIx32"\n", sc->f3);
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usb_debug(" FIELD4\t0x%08"PRIx32"\n", sc->f4);
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SC_DUMP(ROUTE, sc);
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SC_DUMP(SPEED, sc);
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SC_DUMP(MTT, sc);
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SC_DUMP(HUB, sc);
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SC_DUMP(CTXENT, sc);
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SC_DUMP(RHPORT, sc);
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SC_DUMP(NPORTS, sc);
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SC_DUMP(TTID, sc);
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SC_DUMP(TTPORT, sc);
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SC_DUMP(TTT, sc);
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SC_DUMP(UADDR, sc);
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SC_DUMP(STATE, sc);
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}
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void
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xhci_dump_epctx(const epctx_t *const ec)
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{
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xhci_debug("Endpoint Context (@%p):\n", ec);
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usb_debug(" FIELD1\t0x%08"PRIx32"\n", ec->f1);
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usb_debug(" FIELD2\t0x%08"PRIx32"\n", ec->f2);
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usb_debug(" TRDQ_L\t0x%08"PRIx32"\n", ec->tr_dq_low);
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usb_debug(" TRDQ_H\t0x%08"PRIx32"\n", ec->tr_dq_high);
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usb_debug(" FIELD5\t0x%08"PRIx32"\n", ec->f5);
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EC_DUMP(STATE, ec);
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EC_DUMP(INTVAL, ec);
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EC_DUMP(CERR, ec);
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EC_DUMP(TYPE, ec);
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EC_DUMP(MBS, ec);
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EC_DUMP(MPS, ec);
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EC_DUMP(DCS, ec);
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EC_DUMP(AVRTRB, ec);
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EC_DUMP(MXESIT, ec);
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}
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void
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xhci_dump_devctx(const devctx_t *const dc, const u32 ctx_mask)
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{
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int i;
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if (ctx_mask & 1)
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xhci_dump_slotctx(dc->slot);
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for (i = 0; i < SC_GET(CTXENT, dc->slot); ++i) {
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if (ctx_mask & (2 << i))
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xhci_dump_epctx(dc->ep[i]);
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}
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}
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void
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xhci_dump_inputctx(const inputctx_t *const ic)
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{
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xhci_debug("Input Control add: 0x%08"PRIx32"\n", *ic->add);
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xhci_debug("Input Control drop: 0x%08"PRIx32"\n", *ic->drop);
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xhci_dump_devctx(&ic->dev, *ic->add);
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}
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void
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xhci_dump_transfer_trb(const trb_t *const cur)
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{
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xhci_debug("Transfer TRB (@%p):\n", cur);
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usb_debug(" PTR_L\t0x%08"PRIx32"\n", cur->ptr_low);
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usb_debug(" PTR_H\t0x%08"PRIx32"\n", cur->ptr_high);
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usb_debug(" STATUS\t0x%08"PRIx32"\n", cur->status);
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usb_debug(" CNTRL\t0x%08"PRIx32"\n", cur->control);
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TRB_DUMP(TL, cur);
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TRB_DUMP(TDS, cur);
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TRB_DUMP(C, cur);
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TRB_DUMP(ISP, cur);
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TRB_DUMP(CH, cur);
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TRB_DUMP(IOC, cur);
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TRB_DUMP(IDT, cur);
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TRB_DUMP(TT, cur);
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TRB_DUMP(DIR, cur);
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}
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static const trb_t *
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xhci_next_trb(const trb_t *const cur)
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{
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if (TRB_GET(TT, cur) == TRB_LINK)
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return (!cur->ptr_low) ? NULL : phys_to_virt(cur->ptr_low);
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else
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return cur + 1;
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}
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void
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xhci_dump_transfer_trbs(const trb_t *const first, const trb_t *const last)
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{
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const trb_t *cur;
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for (cur = first; cur; cur = xhci_next_trb(cur)) {
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xhci_dump_transfer_trb(cur);
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if (cur == last)
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break;
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}
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}
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#endif
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