Ed Swierk a9a5f49d8f By default, the Intel 3100 LPC interface enables only I/O range 0x3f8 ... for both serial ports, making it challenging to use COM2 for the early console. Enable the traditional I/O ranges 0x3f8 for COM1 and 0x2f8 for COM2. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1		2008-04-30 18:29:35 +00:00
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chip.h	Here is an updated patch addressing most of Uwe's and Peter's	2008-03-16 23:34:10 +00:00
Config.lb	Here is an updated patch addressing most of Uwe's and Peter's	2008-03-16 23:34:10 +00:00
i3100.c	Setting an integrated southbridge device (like SATA or USB2.0) to	2008-04-01 17:14:57 +00:00
i3100.h	Here is an updated patch addressing most of Uwe's and Peter's	2008-03-16 23:34:10 +00:00
i3100_early_lpc.c	By default, the Intel 3100 LPC interface enables only I/O range 0x3f8	2008-04-30 18:29:35 +00:00
i3100_early_smbus.c	The early init code of several Intel southbridge chipsets calls	2008-04-01 02:36:59 +00:00
i3100_ehci.c	Here is an updated patch addressing most of Uwe's and Peter's	2008-03-16 23:34:10 +00:00
i3100_lpc.c	Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots	2008-03-30 11:31:15 +00:00
i3100_pci.c	Here is an updated patch addressing most of Uwe's and Peter's	2008-03-16 23:34:10 +00:00
i3100_reset.c	Here is an updated patch addressing most of Uwe's and Peter's	2008-03-16 23:34:10 +00:00
i3100_sata.c	Setting an integrated southbridge device (like SATA or USB2.0) to	2008-04-01 17:14:57 +00:00
i3100_smbus.c	Here is an updated patch addressing most of Uwe's and Peter's	2008-03-16 23:34:10 +00:00
i3100_smbus.h	Here is an updated patch addressing most of Uwe's and Peter's	2008-03-16 23:34:10 +00:00
i3100_uhci.c	Here is an updated patch addressing most of Uwe's and Peter's	2008-03-16 23:34:10 +00:00