coreboot-kgpe-d16/src/soc
Nico Huber aa4d9b94fd soc/intel/apl: Call mca_configure() on cold boots only
By APL BIOS Spec, we must not do this on warm boots.

The TODO comment seems stale and copied over. So the actual
requirements for SGX are unknown and we add a guard for that
case.

Change-Id: I09b4a2fe22267d7318951aac20a3ea566403492e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31200
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-05 13:27:22 +00:00
..
amd soc/amd/stoneyridge: Reboot if missing MRC cache info 2019-02-04 21:17:57 +00:00
cavium cbmem_top: Fix comment and remove upper limit 2019-01-24 13:54:21 +00:00
imgtec (console,drivers/uart)/Kconfig: Fix dependencies 2018-11-21 22:49:48 +00:00
intel soc/intel/apl: Call mca_configure() on cold boots only 2019-02-05 13:27:22 +00:00
mediatek google/kukui: Move some initialization from bootblock to verstage 2019-01-29 13:10:47 +00:00
nvidia console: Change BOOTBLOCK_CONSOLE default to y 2019-01-14 12:13:55 +00:00
qualcomm console: Change BOOTBLOCK_CONSOLE default to y 2019-01-14 12:13:55 +00:00
rockchip src: Don't use a #defines like Kconfig symbols 2019-01-28 13:41:28 +00:00
samsung src: Don't use a #defines like Kconfig symbols 2019-01-28 13:41:28 +00:00
sifive riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV 2019-01-24 14:21:01 +00:00
ucb riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV 2019-01-24 14:21:01 +00:00