aa6701c090
This removes some duplicate code from Snow's mainboard bootblock by utilizing the bootblock build class. Change-Id: I153247370a8c5127260082dcdca3ebdc5e104fb8 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2270 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
45 lines
1.3 KiB
Makefile
45 lines
1.3 KiB
Makefile
# Run an intermediate step when producing coreboot.rom
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# that adds additional components to the final firmware
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# image outside of CBFS
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#INTERMEDIATE += exynos5250_add_bl1
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# Clock init is done in bootblock to support UART output for
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# debugging. We may add a Kconfig option to disable clock init
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# in the bootblock and try moving it entirely into romstage.
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bootblock-y += clock_init.c
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bootblock-y += clock.c
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romstage-y += clock.c
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romstage-y += clock_init.c
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romstage-y += exynos_cache.c
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romstage-y += lowlevel_init_c.c
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romstage-y += pinmux.c
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romstage-y += power.c
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romstage-y += soc.c
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romstage-y += uart.c
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romstage-y += dmc_common.c
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romstage-y += dmc_init_ddr3.c
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#ramstage-y += clock.c
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#ramstage-y += clock_init.c
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#ramstage-y += power.c
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#ramstage-y += uart.c
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#ramstage-y += pinmux.c
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##ramstage-y += tzpc_init.c
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ramstage-y += clock.c
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ramstage-y += clock_init.c
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ramstage-y += exynos_cache.c
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ramstage-y += lowlevel_init_c.c
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ramstage-y += pinmux.c
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ramstage-y += power.c
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ramstage-y += soc.c
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ramstage-y += uart.c
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#ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c
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#ramstage-$(CONFIG_SATA_AHCI) += sata.c
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ramstage-$(CONFIG_SPL_BUILD) += lowlevel_init_c.c
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exynos5250_add_bl1: $(obj)/coreboot.pre
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printf " DD Adding Samsung Exynos5250 BL1\n"
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dd if=3rdparty/cpu/samsung/exynos5250/E5250.nbl1.bin \
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of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
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