e4d7abc0d4
The devicetree data structures have been available in more than just ramstage and romstage. In order to provide clearer and consistent semantics two new macros are provided: 1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE 2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST The ROMSTAGE_CONST attribute is used in the source code to mark the devicetree data structures as const in early stages even though it's not just romstage. Therefore, rename the attribute to DEVTREE_CONST as that's the actual usage. The only place where the usage was not devicetree related is console_loglevel, but the same name was used for consistency. Any stage that is not ramstage has the const C attribute applied when DEVTREE_CONST is used. Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19333 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
70 lines
1.8 KiB
C
70 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2017 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <device/device.h>
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#include <intelblocks/gspi.h>
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#include <soc/iomap.h>
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#include "chip.h"
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const struct gspi_cfg *gspi_get_soc_cfg(void)
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{
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DEVTREE_CONST struct soc_intel_skylake_config *config;
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int devfn = SA_DEVFN_ROOT;
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DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);
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if (!dev || !dev->chip_info) {
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printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
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__func__);
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return NULL;
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}
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config = dev->chip_info;
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return &config->gspi[0];
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}
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uintptr_t gspi_get_soc_early_base(void)
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{
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return EARLY_GSPI_BASE_ADDRESS;
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}
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/*
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* SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust
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* the bus # accordingly when referring to SPI / GSPI bus numbers.
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*/
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#define GSPI_TO_SPI_BUS(x) (x + 1)
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#define SPI_TO_GSPI_BUS(x) (x - 1)
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int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)
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{
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if (spi_bus == 0)
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return -1;
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*gspi_bus = SPI_TO_GSPI_BUS(spi_bus);
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if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
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return -1;
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return 0;
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}
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int gspi_soc_bus_to_devfn(unsigned int gspi_bus)
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{
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if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)
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return -1;
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return spi_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));
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}
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