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Elyes HAOUAS aa8e7e7776 SPD: fix DDR3 SDRAM memory module types
Correct the definitions for 16b and 32b SO-DIMM modules.
Regarding JEDEC Standard No. 21-C
Annex K: Serial Presence Detect for DDR3 SDRAM Modules (2014),
the hex values used for 16b-SO-DIMM is 0x0c
and for 32b-SO-DIMM module type is 0x0d

Change-Id: I9210ac3409a4aaf55a0f6411d5960cfdca05068d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15262
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2016-06-24 18:15:09 +02:00
3rdparty 3rdparty/arm-trusted-firmware: Update to Jun 8, 2016 master 2016-06-12 12:14:06 +02:00
Documentation Documentation/Intel/Board: Update the Galileo checklist 2016-06-12 12:28:57 +02:00
payloads libpayload/pci: Correct MASK macro names 2016-06-21 20:41:06 +02:00
src SPD: fix DDR3 SDRAM memory module types 2016-06-24 18:15:09 +02:00
util cbfstool: Change CONFIG_FMD_GENPARSER if not set to n 2016-06-21 17:55:17 +02:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore .gitignore: add build and libpayload dirs for nvramcui payload 2016-05-03 04:16:45 +02:00
.gitmodules git modules: rename git submodules to avoid hierarchies 2016-02-11 20:55:55 +01:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: Add myself for Apollolake SoC, FSP2.0, and Amenia mb 2016-05-26 23:52:57 +02:00
Makefile Makefile: Make printall target more readable 2016-06-07 23:31:17 +02:00
Makefile.inc flashmap: Use CONFIG_ROM_SIZE as flash size in flashmap 2016-06-21 17:51:54 +02:00
README README: improve description of compiler requirements 2015-07-30 05:11:33 +02:00
toolchain.inc toolchain.inc: test IASL by version string instead of number 2016-03-04 16:36:25 +01:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.