ab1227226e
Change-Id: If31e7102bf1b47c7ae94b86d981b762eda0a19e5 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/c/25427 Reviewed-by: David Guckian Reviewed-by: King Sumo <kingsumos@gmail.com> Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
107 lines
2.7 KiB
C
107 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2014 - 2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <stdint.h>
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#include <arch/io.h>
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#include <console/console.h>
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#include <intelblocks/pmclib.h>
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#include <soc/iomap.h>
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#include <soc/soc_util.h>
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#include <soc/pm.h>
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const char *const *soc_smi_sts_array(size_t *a)
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{
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static const char *const smi_sts_bits[] = {
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[2] = "BIOS",
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[4] = "SLP_SMI",
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[5] = "APM",
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[6] = "SWSMI_TMR",
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[8] = "PM1",
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[9] = "GPE0",
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[10] = "GPE1",
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[11] = "MC_SMI",
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[12] = "DEVMON",
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[13] = "TCO",
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[14] = "PERIODIC",
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[15] = "SERIRQ",
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[16] = "SMBUS_SMI",
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[17] = "LEGACY_USB2",
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[18] = "INTEL_USB2",
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[19] = "PATCH",
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[20] = "PCI_EXP_SMI",
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[21] = "MONITOR",
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[26] = "SPI",
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[27] = "GPIO_UNLOCK",
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[31] = "LEGACY_USB3",
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};
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*a = ARRAY_SIZE(smi_sts_bits);
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return smi_sts_bits;
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}
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const char *const *soc_tco_sts_array(size_t *a)
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{
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static const char *const tco_sts_bits[] = {
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[0] = "NMI2SMI", [1] = "OS_TCO_SMI",
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[2] = "TCO_INIT", [3] = "TIMEOUT",
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[7] = "NEWCENTURY ", [8] = "BIOSWR ",
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[9] = "CPUSCI ", [10] = "CPUSMI ",
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[12] = "CPUSERR ", [16] = "INTRD_DET ",
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[17] = "SECOND_TO", [20] = "SMLINK_SLV_SMI",
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};
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*a = ARRAY_SIZE(tco_sts_bits);
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return tco_sts_bits;
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}
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uint32_t soc_reset_tco_status(void)
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{
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uint16_t tcobase = get_tcobase();
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uint32_t tco_sts = inl((uint16_t)(tcobase + TCO1_STS));
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uint32_t tco_en = inl((uint16_t)(tcobase + TCO1_CNT));
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outl(tco_sts, (uint16_t)(tcobase + TCO1_STS));
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return tco_sts & tco_en;
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}
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const char *const *soc_std_gpe_sts_array(size_t *a)
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{
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static const char *const gpe_sts_bits[] = {
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[0] = "GPIO_0", [1] = "GPIO_1",
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[2] = "GPIO_2", [3] = "GPIO_3",
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[4] = "GPIO_4", [5] = "GPIO_5",
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[6] = "GPIO_6", [7] = "GPIO_7",
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[8] = "GPIO_8", [9] = "GPIO_9",
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[10] = "GPIO_10", [11] = "GPIO_11",
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[12] = "GPIO_12", [13] = "GPIO_13",
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[14] = "GPIO_14", [15] = "GPIO_15",
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[16] = "GPIO_16", [17] = "GPIO_17",
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[18] = "GPIO_18", [19] = "GPIO_19",
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[20] = "GPIO_20", [21] = "GPIO_21",
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[22] = "GPIO_22", [23] = "GPIO_23",
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[24] = "GPIO_24", [25] = "GPIO_25",
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[26] = "GPIO_26", [27] = "GPIO_27",
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[28] = "GPIO_28", [29] = "GPIO_29",
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[30] = "GPIO_30", [31] = "GPIO_31",
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};
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*a = ARRAY_SIZE(gpe_sts_bits);
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return gpe_sts_bits;
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}
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void clear_pmc_status(void) { /* TODO */ }
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