coreboot-kgpe-d16/src/northbridge/intel/fsp_sandybridge
Vladimir Serbinenko 4337020b95 Remove CACHE_ROM.
With the recent improvement 3d6ffe76f8,
speedup by CACHE_ROM is reduced a lot.
On the other hand this makes coreboot run out of MTRRs depending on
system configuration, hence screwing up I/O access and cache
coherency in worst cases.

CACHE_ROM requires the user to sanity check their boot output because
the feature is brittle. The working configuration is dependent on I/O
hole size, ram size, and chipset. Because of this the current
implementation can leave a system configured in an inconsistent state
leading to unexpected results such as poor performance and/or
inconsistent cache-coherency

Remove this as a buggy feature until we figure out how to do it properly
if necessary.

Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5146
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-25 00:57:35 +01:00
..
acpi intel/*/acpi: Increase range length of MCHBAR buffer to 32 kB 2014-02-24 21:58:08 +01:00
acpi.c
chip.h
early_init.c
finalize.c
fsp_util.c Move hexdump32() to lib/hexdump. 2014-02-11 21:54:34 +01:00
fsp_util.h
gma.c
gma.h
Kconfig Remove CACHE_ROM. 2014-02-25 00:57:35 +01:00
Makefile.inc
mrccache.c lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content 2014-01-12 17:41:02 +01:00
northbridge.c
northbridge.h
raminit.c
raminit.h
report_platform.c
udelay.c