3623eca525
Some Intel SoCs such as Denverton support additional SPI regions for things like Innovation Engine firmware or 10GbE LAN firmwares Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Ia5a450e5002e9f8edee76ca7c2eede9906df36c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> |
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.gitignore | ||
Makefile | ||
Makefile.inc | ||
description.md | ||
ifdtool.c | ||
ifdtool.h |