1095 lines
27 KiB
Plaintext
1095 lines
27 KiB
Plaintext
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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## Copyright (C) 2009-2010 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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mainmenu "coreboot configuration"
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menu "General setup"
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config EXPERT
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bool "Expert mode"
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help
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This allows you to select certain advanced configuration options.
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Warning: Only enable this option if you really know what you are
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doing! You have been warned!
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config LOCALVERSION
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string "Local version string"
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help
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Append an extra string to the end of the coreboot version.
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This can be useful if, for instance, you want to append the
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respective board's hostname or some other identifying string to
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the coreboot version number, so that you can easily distinguish
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boot logs of different boards from each other.
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config CBFS_PREFIX
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string "CBFS prefix to use"
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default "fallback"
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help
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Select the prefix to all files put into the image. It's "fallback"
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by default, "normal" is a common alternative.
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config ALT_CBFS_LOAD_PAYLOAD
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bool "Use alternative cbfs_load_payload() implementation."
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default n
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help
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Either board or southbridge provide an alternative cbfs_load_payload()
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implementation. This may be used, for example, if accessing the ROM
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through memory-mapped I/O is slow and a faster alternative can be
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provided.
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choice
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prompt "Compiler to use"
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default COMPILER_GCC
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help
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This option allows you to select the compiler used for building
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coreboot.
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config COMPILER_GCC
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bool "GCC"
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help
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Use the GNU Compiler Collection (GCC) to build coreboot.
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For details see http://gcc.gnu.org.
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config COMPILER_LLVM_CLANG
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bool "LLVM/clang"
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help
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Use LLVM/clang to build coreboot.
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For details see http://clang.llvm.org.
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endchoice
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config SCANBUILD_ENABLE
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bool "Build with scan-build for static code analysis"
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default n
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help
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Changes the build process to use scan-build (a utility for
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running the clang static code analyzer from the command line).
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Requires the scan-build utility in your system $PATH.
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For details see http://clang-analyzer.llvm.org/scan-build.html.
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config SCANBUILD_REPORT_LOCATION
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string "Directory for the scan-build report(s)"
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default ""
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depends on SCANBUILD_ENABLE
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help
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Directory where the scan-build reports should be stored in. The
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reports are stored in subdirectories of the form 'yyyy-mm-dd-*'
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in the specified directory.
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If this setting is left empty, the coreboot top-level directory
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will be used to store the report subdirectories.
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config CCACHE
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bool "Use ccache to speed up (re)compilation"
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default n
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help
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Enables the use of ccache for faster builds.
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Requires the ccache utility in your system $PATH.
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For details see https://ccache.samba.org.
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config SCONFIG_GENPARSER
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bool "Generate SCONFIG parser using flex and bison"
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default n
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depends on EXPERT
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help
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Enable this option if you are working on the sconfig device tree
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parser and made changes to sconfig.l and sconfig.y.
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Otherwise, say N.
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config USE_OPTION_TABLE
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bool "Use CMOS for configuration values"
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default n
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depends on HAVE_OPTION_TABLE
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help
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Enable this option if coreboot shall read options from the "CMOS"
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NVRAM instead of using hard-coded values.
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config COMPRESS_RAMSTAGE
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bool "Compress ramstage with LZMA"
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default y
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help
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Compress ramstage to save memory in the flash image. Note
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that decompression might slow down booting if the boot flash
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is connected through a slow link (i.e. SPI).
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config INCLUDE_CONFIG_FILE
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bool "Include the coreboot .config file into the ROM image"
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default y
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help
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Include the .config file that was used to compile coreboot
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in the (CBFS) ROM image. This is useful if you want to know which
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options were used to build a specific coreboot.rom image.
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Saying Y here will increase the image size by 2-3kB.
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You can use the following command to easily list the options:
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grep -a CONFIG_ coreboot.rom
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Alternatively, you can also use cbfstool to print the image
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contents (including the raw 'config' item we're looking for).
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Example:
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$ cbfstool coreboot.rom print
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coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
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offset 0x0
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Alignment: 64 bytes
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Name Offset Type Size
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cmos_layout.bin 0x0 cmos layout 1159
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fallback/romstage 0x4c0 stage 339756
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fallback/coreboot_ram 0x53440 stage 186664
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fallback/payload 0x80dc0 payload 51526
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config 0x8d740 raw 3324
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(empty) 0x8e480 null 3610440
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config EARLY_CBMEM_INIT
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bool
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default n
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help
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Make coreboot initialize the CBMEM structures while running in ROM
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stage. This is useful when the ROM stage wants to communicate
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some, for instance, execution timestamps. It needs support in
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romstage.c and should be enabled by the board's Kconfig.
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config DYNAMIC_CBMEM
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bool "The CBMEM space is dynamically grown."
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default n
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select EARLY_CBMEM_INIT
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help
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Instead of reserving a static amount of CBMEM space the CBMEM
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area grows dynamically. CBMEM can be used both in romstage (after
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memory initialization) and ramstage.
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config COLLECT_TIMESTAMPS
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bool "Create a table of timestamps collected during boot"
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default n
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help
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Make coreboot create a table of timer-ID/timer-value pairs to
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allow measuring time spent at different phases of the boot process.
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config USE_BLOBS
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bool "Allow use of binary-only repository"
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default n
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help
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This draws in the blobs repository, which contains binary files that
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might be required for some chipsets or boards.
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This flag ensures that a "Free" option remains available for users.
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config COVERAGE
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bool "Code coverage support"
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depends on COMPILER_GCC
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default n
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help
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Add code coverage support for coreboot. This will store code
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coverage information in CBMEM for extraction from user space.
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If unsure, say N.
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endmenu
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source src/mainboard/Kconfig
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# This option is used to set the architecture of a mainboard to X86.
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# It is usually set in mainboard/*/Kconfig.
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config ARCH_X86
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bool
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default n
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select PCI
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config ARCH_ARMV7
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bool
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default n
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# Warning: The file is included whether or not the if is here.
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# but the if controls how the evaluation occurs.
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if ARCH_X86
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source src/arch/x86/Kconfig
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endif
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if ARCH_ARMV7
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source src/arch/armv7/Kconfig
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endif
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config HAVE_ARCH_MEMSET
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bool
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default n
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config HAVE_ARCH_MEMCPY
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bool
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default n
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config HAVE_ARCH_MEMMOVE
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bool
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default n
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menu "Chipset"
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comment "CPU"
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source src/cpu/Kconfig
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comment "Northbridge"
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source src/northbridge/Kconfig
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comment "Southbridge"
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source src/southbridge/Kconfig
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comment "Super I/O"
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source src/superio/Kconfig
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comment "Embedded Controllers"
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source src/ec/Kconfig
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endmenu
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source src/device/Kconfig
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menu "Generic Drivers"
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source src/drivers/Kconfig
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endmenu
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config HEAP_SIZE
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hex
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default 0x4000
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config MAX_CPUS
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int
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default 1
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config MMCONF_SUPPORT_DEFAULT
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bool
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default n
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config MMCONF_SUPPORT
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bool
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default n
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source src/console/Kconfig
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# This should default to N and be set by SuperI/O drivers that have an UART
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config HAVE_UART_IO_MAPPED
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bool
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default y if ARCH_X86
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default n if ARCH_ARMV7
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config HAVE_UART_MEMORY_MAPPED
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bool
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default n
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config HAVE_UART_SPECIAL
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bool
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default n
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config HAVE_ACPI_RESUME
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bool
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default n
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config HAVE_ACPI_SLIC
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bool
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default n
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config ACPI_SSDTX_NUM
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int
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default 0
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config HAVE_HARD_RESET
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bool
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default n
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help
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This variable specifies whether a given board has a hard_reset
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function, no matter if it's provided by board code or chipset code.
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config HAVE_INIT_TIMER
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bool
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default n if UDELAY_IO
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default y
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config HAVE_MONOTONIC_TIMER
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def_bool n
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help
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The board/chipset provides a monotonic timer.
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config TIMER_QUEUE
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def_bool n
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depends on HAVE_MONOTONIC_TIMER
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help
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Provide a timer queue for performing time-based callbacks.
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config COOP_MULTITASKING
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def_bool n
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depends on TIMER_QUEUE && ARCH_X86
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help
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Cooperative multitasking allows callbacks to be multiplexed on the
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main thread of ramstage. With this enabled it allows for multiple
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execution paths to take place when they have udelay() calls within
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their code.
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config NUM_THREADS
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int
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default 4
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depends on COOP_MULTITASKING
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help
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How many execution threads to cooperatively multitask with.
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config HIGH_SCRATCH_MEMORY_SIZE
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hex
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default 0x0
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config HAVE_OPTION_TABLE
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bool
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default n
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help
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This variable specifies whether a given board has a cmos.layout
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file containing NVRAM/CMOS bit definitions.
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It defaults to 'n' but can be selected in mainboard/*/Kconfig.
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config PIRQ_ROUTE
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bool
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default n
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config HAVE_SMI_HANDLER
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bool
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default n
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config PCI_IO_CFG_EXT
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bool
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default n
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config IOAPIC
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bool
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default n
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config CBFS_SIZE
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hex
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default ROM_SIZE
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config CACHE_ROM_SIZE
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hex
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default CBFS_SIZE
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# TODO: Can probably be removed once all chipsets have kconfig options for it.
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config VIDEO_MB
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int
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default 0
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config USE_WATCHDOG_ON_BOOT
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bool
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default n
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config VGA
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bool
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default n
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help
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Build board-specific VGA code.
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config GFXUMA
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bool
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default n
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help
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Enable Unified Memory Architecture for graphics.
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config RELOCATABLE_MODULES
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bool "Relocatable Modules"
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default n
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help
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If RELOCATABLE_MODULES is selected then support is enabled for
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building relocatable modules in the ram stage. Those modules can be
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loaded anywhere and all the relocations are handled automatically.
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config RELOCATABLE_RAMSTAGE
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depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM)
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bool "Build the ramstage to be relocatable in 32-bit address space."
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default n
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help
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The reloctable ramstage support allows for the ramstage to be built
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as a relocatable module. The stage loader can identify a place
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out of the OS way so that copying memory is unnecessary during an S3
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wake. When selecting this option the romstage is responsible for
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determing a stack location to use for loading the ramstage.
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config HAVE_ACPI_TABLES
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bool
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help
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This variable specifies whether a given board has ACPI table support.
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It is usually set in mainboard/*/Kconfig.
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Whether or not the ACPI tables are actually generated by coreboot
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is configurable by the user via GENERATE_ACPI_TABLES.
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config HAVE_MP_TABLE
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bool
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help
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This variable specifies whether a given board has MP table support.
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It is usually set in mainboard/*/Kconfig.
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Whether or not the MP table is actually generated by coreboot
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is configurable by the user via GENERATE_MP_TABLE.
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config HAVE_PIRQ_TABLE
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bool
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help
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This variable specifies whether a given board has PIRQ table support.
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It is usually set in mainboard/*/Kconfig.
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Whether or not the PIRQ table is actually generated by coreboot
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is configurable by the user via GENERATE_PIRQ_TABLE.
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config MAX_PIRQ_LINKS
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int
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default 4
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help
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This variable specifies the number of PIRQ interrupt links which are
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routable. On most chipsets, this is 4, INTA through INTD. Some
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chipsets offer more than four links, commonly up to INTH. They may
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also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
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table specifies links greater than 4, pirq_route_irqs will not
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function properly, unless this variable is correctly set.
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#These Options are here to avoid "undefined" warnings.
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#The actual selection and help texts are in the following menu.
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menu "System tables"
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config MULTIBOOT
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bool "Generate Multiboot tables (for GRUB2)"
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default y
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depends on ARCH_X86
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config GENERATE_ACPI_TABLES
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prompt "Generate ACPI tables" if HAVE_ACPI_TABLES
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bool
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default HAVE_ACPI_TABLES
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help
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Generate ACPI tables for this board.
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If unsure, say Y.
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config GENERATE_MP_TABLE
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prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
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bool
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default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
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help
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Generate an MP table (conforming to the Intel MultiProcessor
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specification 1.4) for this board.
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If unsure, say Y.
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config GENERATE_PIRQ_TABLE
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prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
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bool
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default HAVE_PIRQ_TABLE
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help
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Generate a PIRQ table for this board.
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If unsure, say Y.
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config GENERATE_SMBIOS_TABLES
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depends on ARCH_X86
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bool "Generate SMBIOS tables"
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default y
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help
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Generate SMBIOS tables for this board.
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If unsure, say Y.
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endmenu
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menu "Payload"
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choice
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prompt "Add a payload"
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default PAYLOAD_NONE if !ARCH_X86
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default PAYLOAD_SEABIOS if ARCH_X86
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config PAYLOAD_NONE
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bool "None"
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help
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Select this option if you want to create an "empty" coreboot
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ROM image for a certain mainboard, i.e. a coreboot ROM image
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which does not yet contain a payload.
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For such an image to be useful, you have to use 'cbfstool'
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to add a payload to the ROM image later.
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config PAYLOAD_ELF
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bool "An ELF executable payload"
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help
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Select this option if you have a payload image (an ELF file)
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which coreboot should run as soon as the basic hardware
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initialization is completed.
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You will be able to specify the location and file name of the
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payload image later.
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config PAYLOAD_LINUX
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bool "A Linux payload"
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help
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Select this option if you have a Linux bzImage which coreboot
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should run as soon as the basic hardware initialization
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is completed.
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You will be able to specify the location and file name of the
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payload image later.
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config PAYLOAD_SEABIOS
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bool "SeaBIOS"
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depends on ARCH_X86
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help
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Select this option if you want to build a coreboot image
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with a SeaBIOS payload. If you don't know what this is
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about, just leave it enabled.
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See http://coreboot.org/Payloads for more information.
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config PAYLOAD_FILO
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bool "FILO"
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help
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Select this option if you want to build a coreboot image
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with a FILO payload. If you don't know what this is
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about, just leave it enabled.
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See http://coreboot.org/Payloads for more information.
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config PAYLOAD_GRUB2
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bool "GRUB2"
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help
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Select this option if you want to build a coreboot image
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with a GRUB2 payload. If you don't know what this is
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about, just leave it enabled.
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See http://coreboot.org/Payloads for more information.
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|
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config PAYLOAD_TIANOCORE
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bool "Tiano Core"
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help
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|
Select this option if you want to build a coreboot image
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|
with a Tiano Core payload. If you don't know what this is
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about, just leave it enabled.
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See http://coreboot.org/Payloads for more information.
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endchoice
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choice
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prompt "SeaBIOS version"
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default SEABIOS_STABLE
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depends on PAYLOAD_SEABIOS
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|
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config SEABIOS_STABLE
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bool "1.7.2.1"
|
|
help
|
|
Stable SeaBIOS version
|
|
config SEABIOS_MASTER
|
|
bool "master"
|
|
help
|
|
Newest SeaBIOS version
|
|
endchoice
|
|
|
|
config SEABIOS_PS2_TIMEOUT
|
|
prompt "PS/2 keyboard controller initialization timeout (milliseconds)" if PAYLOAD_SEABIOS
|
|
default 0
|
|
depends on EXPERT
|
|
int
|
|
help
|
|
Some PS/2 keyboard controllers don't respond to commands immediately
|
|
after powering on. This specifies how long SeaBIOS will wait for the
|
|
keyboard controller to become ready before giving up.
|
|
|
|
choice
|
|
prompt "GRUB2 version"
|
|
default GRUB2_MASTER
|
|
depends on PAYLOAD_GRUB2
|
|
|
|
config GRUB2_MASTER
|
|
bool "HEAD"
|
|
help
|
|
Newest GRUB2 version
|
|
endchoice
|
|
|
|
choice
|
|
prompt "FILO version"
|
|
default FILO_STABLE
|
|
depends on PAYLOAD_FILO
|
|
|
|
config FILO_STABLE
|
|
bool "0.6.0"
|
|
help
|
|
Stable FILO version
|
|
config FILO_MASTER
|
|
bool "HEAD"
|
|
help
|
|
Newest FILO version
|
|
endchoice
|
|
|
|
config PAYLOAD_FILE
|
|
string "Payload path and filename"
|
|
depends on PAYLOAD_ELF
|
|
default "payload.elf"
|
|
help
|
|
The path and filename of the ELF executable file to use as payload.
|
|
|
|
config PAYLOAD_FILE
|
|
string "Linux path and filename"
|
|
depends on PAYLOAD_LINUX
|
|
default "bzImage"
|
|
help
|
|
The path and filename of the bzImage kernel to use as payload.
|
|
|
|
config PAYLOAD_FILE
|
|
depends on PAYLOAD_SEABIOS
|
|
default "$(obj)/seabios/out/bios.bin.elf"
|
|
|
|
config PAYLOAD_FILE
|
|
depends on PAYLOAD_FILO
|
|
default "payloads/external/FILO/filo/build/filo.elf"
|
|
|
|
config PAYLOAD_FILE
|
|
depends on PAYLOAD_GRUB2
|
|
default "payloads/external/GRUB2/grub2/build/default_payload.elf"
|
|
|
|
config PAYLOAD_FILE
|
|
string "Tianocore firmware volume"
|
|
depends on PAYLOAD_TIANOCORE
|
|
default "COREBOOT.fd"
|
|
help
|
|
The result of a corebootPkg build
|
|
|
|
# TODO: Defined if no payload? Breaks build?
|
|
config COMPRESSED_PAYLOAD_LZMA
|
|
bool "Use LZMA compression for payloads"
|
|
default y
|
|
depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO || PAYLOAD_TIANOCORE || PAYLOAD_GRUB2
|
|
help
|
|
In order to reduce the size payloads take up in the ROM chip
|
|
coreboot can compress them using the LZMA algorithm.
|
|
|
|
config LINUX_COMMAND_LINE
|
|
string "Linux command line"
|
|
depends on PAYLOAD_LINUX
|
|
default ""
|
|
help
|
|
A command line to add to the Linux kernel.
|
|
|
|
config LINUX_INITRD
|
|
string "Linux initrd"
|
|
depends on PAYLOAD_LINUX
|
|
default ""
|
|
help
|
|
An initrd image to add to the Linux kernel.
|
|
|
|
endmenu
|
|
|
|
menu "Debugging"
|
|
|
|
# TODO: Better help text and detailed instructions.
|
|
config GDB_STUB
|
|
bool "GDB debugging support"
|
|
default n
|
|
help
|
|
If enabled, you will be able to set breakpoints for gdb debugging.
|
|
See src/arch/x86/lib/c_start.S for details.
|
|
|
|
config GDB_WAIT
|
|
bool "Wait for a GDB connection"
|
|
default n
|
|
depends on GDB_STUB
|
|
help
|
|
If enabled, coreboot will wait for a GDB connection.
|
|
|
|
config DEBUG_CBFS
|
|
bool "Output verbose CBFS debug messages"
|
|
default n
|
|
help
|
|
This option enables additional CBFS related debug messages.
|
|
|
|
config HAVE_DEBUG_RAM_SETUP
|
|
def_bool n
|
|
|
|
config DEBUG_RAM_SETUP
|
|
bool "Output verbose RAM init debug messages"
|
|
default n
|
|
depends on HAVE_DEBUG_RAM_SETUP
|
|
help
|
|
This option enables additional RAM init related debug messages.
|
|
It is recommended to enable this when debugging issues on your
|
|
board which might be RAM init related.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config HAVE_DEBUG_CAR
|
|
def_bool n
|
|
|
|
config DEBUG_CAR
|
|
def_bool n
|
|
depends on HAVE_DEBUG_CAR
|
|
|
|
if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
config DEBUG_CAR
|
|
bool "Output verbose Cache-as-RAM debug messages"
|
|
default n
|
|
depends on HAVE_DEBUG_CAR
|
|
help
|
|
This option enables additional CAR related debug messages.
|
|
endif
|
|
|
|
config DEBUG_PIRQ
|
|
bool "Check PIRQ table consistency"
|
|
default n
|
|
depends on GENERATE_PIRQ_TABLE
|
|
help
|
|
If unsure, say N.
|
|
|
|
config HAVE_DEBUG_SMBUS
|
|
def_bool n
|
|
|
|
config DEBUG_SMBUS
|
|
bool "Output verbose SMBus debug messages"
|
|
default n
|
|
depends on HAVE_DEBUG_SMBUS
|
|
help
|
|
This option enables additional SMBus (and SPD) debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config DEBUG_SMI
|
|
bool "Output verbose SMI debug messages"
|
|
default n
|
|
depends on HAVE_SMI_HANDLER
|
|
help
|
|
This option enables additional SMI related debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config DEBUG_SMM_RELOCATION
|
|
bool "Debug SMM relocation code"
|
|
default n
|
|
depends on HAVE_SMI_HANDLER
|
|
help
|
|
This option enables additional SMM handler relocation related
|
|
debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
config DEBUG_MALLOC
|
|
prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
bool
|
|
default n
|
|
help
|
|
This option enables additional malloc related debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
config DEBUG_ACPI
|
|
prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
bool
|
|
default n
|
|
help
|
|
This option enables additional ACPI related debug messages.
|
|
|
|
Note: This option will slightly increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
|
|
# printk(BIOS_DEBUG, ...) calls.
|
|
config REALMODE_DEBUG
|
|
prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
|
|
bool
|
|
default n
|
|
depends on PCI_OPTION_ROM_RUN_REALMODE
|
|
help
|
|
This option enables additional x86emu related debug messages.
|
|
|
|
Note: This option will increase the time to emulate a ROM.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG
|
|
bool "Output verbose x86emu debug messages"
|
|
default n
|
|
depends on PCI_OPTION_ROM_RUN_YABEL
|
|
help
|
|
This option enables additional x86emu related debug messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_JMP
|
|
bool "Trace JMP/RETF"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print information about JMP and RETF opcodes from x86emu.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_TRACE
|
|
bool "Trace all opcodes"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print _all_ opcodes that are executed by x86emu.
|
|
|
|
WARNING: This will produce a LOT of output and take a long time.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_PNP
|
|
bool "Log Plug&Play accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print Plug And Play accesses made by option ROMs.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_DISK
|
|
bool "Log Disk I/O"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print Disk I/O related messages.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_PMM
|
|
bool "Log PMM"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to POST Memory Manager (PMM).
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
|
|
config X86EMU_DEBUG_VBE
|
|
bool "Debug VESA BIOS Extensions"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to VESA BIOS Extension (VBE) functions.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_INT10
|
|
bool "Redirect INT10 output to console"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Let INT10 (i.e. character output) calls print messages to debug output.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_INTERRUPTS
|
|
bool "Log intXX calls"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to interrupt handling.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_CHECK_VMEM_ACCESS
|
|
bool "Log special memory accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print messages related to accesses to certain areas of the virtual
|
|
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_MEM
|
|
bool "Log all memory accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print memory accesses made by option ROM.
|
|
Note: This also includes accesses to fetch instructions.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_IO
|
|
bool "Log IO accesses"
|
|
default n
|
|
depends on X86EMU_DEBUG
|
|
help
|
|
Print I/O accesses made by option ROM.
|
|
|
|
Note: This option will increase the size of the coreboot image.
|
|
|
|
If unsure, say N.
|
|
|
|
config X86EMU_DEBUG_TIMINGS
|
|
bool "Output timing information"
|
|
default n
|
|
depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
|
|
help
|
|
Print timing information needed by i915tool.
|
|
|
|
If unsure, say N.
|
|
|
|
config DEBUG_TPM
|
|
bool "Output verbose TPM debug messages"
|
|
default n
|
|
depends on TPM
|
|
help
|
|
This option enables additional TPM related debug messages.
|
|
|
|
config DEBUG_SPI_FLASH
|
|
bool "Output verbose SPI flash debug messages"
|
|
default n
|
|
depends on SPI_FLASH
|
|
help
|
|
This option enables additional SPI flash related debug messages.
|
|
|
|
config DEBUG_USBDEBUG
|
|
bool "Output verbose USB 2.0 EHCI debug dongle messages"
|
|
default n
|
|
depends on USBDEBUG
|
|
help
|
|
This option enables additional USB 2.0 debug dongle related messages.
|
|
|
|
Select this to debug the connection of usbdebug dongle. Note that
|
|
you need some other working console to receive the messages.
|
|
|
|
if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
|
|
# Only visible with the right southbridge and loglevel.
|
|
config DEBUG_INTEL_ME
|
|
bool "Verbose logging for Intel Management Engine"
|
|
default n
|
|
help
|
|
Enable verbose logging for Intel Management Engine driver that
|
|
is present on Intel 6-series chipsets.
|
|
endif
|
|
|
|
config TRACE
|
|
bool "Trace function calls"
|
|
default n
|
|
help
|
|
If enabled, every function will print information to console once
|
|
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
|
|
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
|
|
of calling function. Please note some printk releated functions
|
|
are omitted from trace to have good looking console dumps.
|
|
|
|
config DEBUG_COVERAGE
|
|
bool "Debug code coverage"
|
|
default n
|
|
depends on COVERAGE
|
|
help
|
|
If enabled, the code coverage hooks in coreboot will output some
|
|
information about the coverage data that is dumped.
|
|
|
|
endmenu
|
|
|
|
# These probably belong somewhere else, but they are needed somewhere.
|
|
config RAMINIT_SYSINFO
|
|
bool
|
|
default n
|
|
|
|
config ENABLE_APIC_EXT_ID
|
|
bool
|
|
default n
|
|
|
|
config WARNINGS_ARE_ERRORS
|
|
bool
|
|
default y
|
|
|
|
# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
|
|
# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
|
|
# mutually exclusive. One of these options must be selected in the
|
|
# mainboard Kconfig if the chipset supports enabling and disabling of
|
|
# the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
|
|
# in mainboard/Kconfig to know if the button should be enabled or not.
|
|
|
|
config POWER_BUTTON_DEFAULT_ENABLE
|
|
def_bool n
|
|
help
|
|
Select when the board has a power button which can optionally be
|
|
disabled by the user.
|
|
|
|
config POWER_BUTTON_DEFAULT_DISABLE
|
|
def_bool n
|
|
help
|
|
Select when the board has a power button which can optionally be
|
|
enabled by the user, e.g. when the board ships with a jumper over
|
|
the power switch contacts.
|
|
|
|
config POWER_BUTTON_FORCE_ENABLE
|
|
def_bool n
|
|
help
|
|
Select when the board requires that the power button is always
|
|
enabled.
|
|
|
|
config POWER_BUTTON_FORCE_DISABLE
|
|
def_bool n
|
|
help
|
|
Select when the board requires that the power button is always
|
|
disabled, e.g. when it has been hardwired to ground.
|
|
|
|
config POWER_BUTTON_IS_OPTIONAL
|
|
bool
|
|
default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
|
|
default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
|
|
help
|
|
Internal option that controls ENABLE_POWER_BUTTON visibility.
|
|
|
|
source src/vendorcode/Kconfig
|