a0c68f864e
* Don't implicitly add __PRE_RAM__ in romcc. Fixes intel/xe7501devkit Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define ASSEMBLY 1
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#define __PRE_RAM__
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "lib/ramtest.c"
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#include "northbridge/amd/gx1/raminit.c"
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#include "superio/nsc/pc97317/pc97317_early_serial.c"
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#include "cpu/x86/bist.h"
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#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
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#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
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static void main(unsigned long bist)
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{
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pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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uart_init();
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console_init();
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report_bist_failure(bist);
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cs5530_enable_rom();
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sdram_init();
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/* ram_check(0, 640 * 1024); */
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}
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