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Subrata Banik ac1b1dd83e util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH
This patch performs below operations:
1. Remove reserved NR field from Gen 5 onwards SPI programming guide
2. Convert ISL to PSL as applicable for Gen 5 onwards PCH
3. Skip FLMAP2 register dump due to nonuniformity since Gen 5 onwards PCH
4. Dump FLILL1 register as applicable for Gen 5 onwards PCH
5. Remove FLPB register as not applicable since Gen 5 PCH

BUG=b:153888802
TEST=Dump FD for Hatch platform as below
> ifdtool -d coreboot.rom

PCH Revision: 300 series Cannon Point/ 400 series Ice Point
FLMAP0:    0x00040003
  FRBA:    0x40
  NC:      1
  FCBA:    0x30
FLMAP1:    0x45100208
  PSL:     0x45
  FPSBA:   0x100
  NM:      2
  FMBA:    0x80

FLILL1     0xc7c4b9b7
  Invalid Instruction 7: 0xc7
  Invalid Instruction 6: 0xc4
  Invalid Instruction 5: 0xb9
  Invalid Instruction 4: 0xb7

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I5141ae5dd174659fde5401fac313a701ae4f8f44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-02 07:17:25 +00:00
3rdparty Update arm-trusted-firmware submodule to upstream master 2020-08-31 06:39:15 +00:00
Documentation Documentation: Discuss how we use language 2020-08-31 20:23:22 +00:00
LICENSES drivers: Use SPDX identifiers 2020-05-25 22:19:21 +00:00
configs configs: Build test experimental x86_64 code 2020-08-19 10:54:45 +00:00
payloads xhci: Do not set the CRCR_CS bit 2020-08-31 06:38:53 +00:00
src mb/google/sarien/Kconfig: Drop redundant 'select TPM2' 2020-09-02 07:17:08 +00:00
tests tests: Improve test_skip_atoi() in /lib/string-test test case 2020-07-12 19:38:39 +00:00
util util/ifdtool: Fix miscellaneous IFD offset since Gen 5 PCH 2020-09-02 07:17:25 +00:00
.checkpatch.conf .checkpatch.conf: Ignore a few more warnings 2018-08-13 12:23:24 +00:00
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.editorconfig Add .editorconfig file 2019-09-10 12:52:18 +00:00
.gitignore gitignore: Remove obsolete paths 2020-08-31 06:41:23 +00:00
.gitmodules Add qc_blobs repository 2020-06-30 08:57:03 +00:00
.gitreview
AUTHORS AUTHORS, util/: Drop individual copyright notices 2020-05-09 21:21:32 +00:00
COPYING
MAINTAINERS MAINTAINERS: Update soc/mediatek maintainership 2020-08-26 07:35:21 +00:00
Makefile build system: Rely on xcompile for HOSTCC and HOSTCXX 2020-07-08 08:53:46 +00:00
Makefile.inc Makefile.inc: Print warning type ignored by IASL 2020-08-31 06:44:31 +00:00
README.md README.md: Remove link to deprecated wiki 2019-11-16 20:39:55 +00:00
gnat.adc treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
toolchain.inc Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTION 2020-05-26 15:04:08 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.