c4f9f4bdae
Several SPD hex files for chell were missing from upstream coreboot (as compared to the Chromium tree/branch), which resulted in the incorrect type and amount of RAM being reported on chell boards with > 4GB RAM. Add these missing files and their Makefile entries. TEST: boot google/chell m7/16GB config and observe correct RAM type and amount reported via dmidecode and cbmem console log. Change-Id: I37d708c96e754b438e40fc413420aa64bf234c29 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22402 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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.. | ||
acpi | ||
spd | ||
acpi_tables.c | ||
board_info.txt | ||
bootblock_mainboard.c | ||
chromeos.c | ||
chromeos.fmd | ||
cmos.layout | ||
devicetree.cb | ||
dsdt.asl | ||
ec.c | ||
ec.h | ||
gpio.h | ||
Kconfig | ||
Kconfig.name | ||
mainboard.c | ||
Makefile.inc | ||
pei_data.c | ||
ramstage.c | ||
romstage.c | ||
smihandler.c |