76cedd2c29
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
167 lines
4.6 KiB
C
167 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <acpi/acpi.h>
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#include <cbmem.h>
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#include <cpu/x86/smm.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/smm.h>
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#include <fsp/util.h>
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#include <soc/iomap.h>
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#include <soc/iosf.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <stddef.h>
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/*
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* Host Memory Map:
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*
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* +--------------------------+ BMBOUND_HI
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* | Usable DRAM |
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* +--------------------------+ 4GiB
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* | PCI Address Space |
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* +--------------------------+ BMBOUND
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* | TPM |
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* +--------------------------+ IMR2
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* | TXE |
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* +--------------------------+ IMR1
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* | iGD |
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* +--------------------------+
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* | GTT |
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* +--------------------------+ SMMRRH, IRM0
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* | TSEG |
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* +--------------------------+ SMMRRL
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* | Usable DRAM |
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* +--------------------------+ 0
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*
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* Note that there are really only a few regions that need to enumerated w.r.t.
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* coreboot's resource model:
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*
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* +--------------------------+ BMBOUND_HI
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* | Cacheable/Usable |
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* +--------------------------+ 4GiB
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*
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* +--------------------------+ BMBOUND
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* | Uncacheable/Reserved |
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* +--------------------------+ SMMRRH
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* | Cacheable/Reserved |
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* +--------------------------+ SMMRRL
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* | Cacheable/Usable |
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* +--------------------------+ 0
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*/
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#define RES_IN_KIB(r) ((r) >> 10)
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uint32_t nc_read_top_of_low_memory(void)
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{
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MAYBE_STATIC_BSS uint32_t tolm = 0;
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if (tolm)
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return tolm;
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tolm = iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1);
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return tolm;
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}
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static void nc_read_resources(struct device *dev)
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{
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unsigned long mmconf;
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unsigned long bmbound_k;
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unsigned long bmbound_hi;
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uintptr_t smm_base;
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size_t smm_size;
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unsigned long tseg_base_k;
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unsigned long tseg_top_k;
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unsigned long fsp_res_base_k;
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unsigned long base_k, size_k;
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const unsigned long four_gig_kib = (4 << (30 - 10));
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void *fsp_reserved_memory_area;
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int index = 0;
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/* Read standard PCI resources. */
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pci_dev_read_resources(dev);
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/* Determine TSEG data */
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smm_region(&smm_base, &smm_size);
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tseg_base_k = RES_IN_KIB(smm_base);
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tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size);
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/* Determine the base of the FSP reserved memory */
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fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);
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if (fsp_reserved_memory_area) {
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fsp_res_base_k =
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RES_IN_KIB((unsigned int)fsp_reserved_memory_area);
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} else {
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/* If no FSP reserverd area */
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fsp_res_base_k = tseg_base_k;
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}
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/* PCIe memory-mapped config space access - 256 MiB. */
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mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
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mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KIB(mmconf), 256 * 1024);
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/* 0 -> 0xa0000 */
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base_k = RES_IN_KIB(0);
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size_k = RES_IN_KIB(0xa0000) - base_k;
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ram_resource(dev, index++, base_k, size_k);
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/* High memory -> fsp_res_base - cacheable and usable */
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base_k = RES_IN_KIB(0x100000);
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size_k = fsp_res_base_k - base_k;
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ram_resource(dev, index++, base_k, size_k);
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/* fsp_res_base -> tseg_top - Reserved */
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base_k = fsp_res_base_k;
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size_k = tseg_top_k - base_k;
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reserved_ram_resource(dev, index++, base_k, size_k);
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/* TSEG TOP -> bmbound is memory backed mmio. */
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bmbound_k = RES_IN_KIB(nc_read_top_of_low_memory());
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mmio_resource(dev, index++, tseg_top_k, bmbound_k - tseg_top_k);
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/*
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* The BMBOUND_HI register matches register bits of 31:24 with address
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* bits of 35:28. Therefore, shift register to align properly.
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*/
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bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1);
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bmbound_hi = RES_IN_KIB(bmbound_hi) << 4;
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if (bmbound_hi > four_gig_kib)
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ram_resource(dev, index++, four_gig_kib,
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bmbound_hi - four_gig_kib);
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/*
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* Reserve everything between A segment and 1MB:
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*
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* 0xa0000 - 0xbffff: legacy VGA
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* 0xc0000 - 0xfffff: RAM
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*/
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mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
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reserved_ram_resource(dev, index++, (0xc0000 >> 10),
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(0x100000 - 0xc0000) >> 10);
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/*
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* Reserve local APIC
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*/
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base_k = RES_IN_KIB(LAPIC_DEFAULT_BASE);
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size_k = RES_IN_KIB(0x00100000);
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mmio_resource(dev, index++, base_k, size_k);
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if (CONFIG(CHROMEOS))
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chromeos_reserve_ram_oops(dev, index++);
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}
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static struct device_operations nc_ops = {
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.acpi_fill_ssdt = generate_cpu_entries,
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.read_resources = nc_read_resources,
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.ops_pci = &soc_pci_ops,
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};
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static const struct pci_driver nc_driver __pci_driver = {
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.ops = &nc_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = SOC_DEVID,
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};
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