acb9c0b661
Remove some CamelCase in acpi.c Add FSP PcdDvfsEnable configuration parameter. Add lpc_init and lpc_set_low_power routines. Remove Braswell reference to make code easier to port to another SOC. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I5063215fc5d19b4a07f3161f76bf3d58e30f6f02 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10768 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
125 lines
3.9 KiB
C
125 lines
3.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <soc/gpio.h>
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#include <soc/pm.h>
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#include <soc/iomap.h>
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#define SUSPEND_CYCLE 1
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#define RESUME_CYCLE 0
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#define LPC_FAMILY_NUMBER(gpio_pad) (gpio_pad / MAX_FAMILY_PAD_GPIO_NO)
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#define LPC_INTERNAL_PAD_NUM(gpio_pad) (gpio_pad % MAX_FAMILY_PAD_GPIO_NO)
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#define LPC_GPIO_OFFSET(gpio_pad) (FAMILY_PAD_REGS_OFF \
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+ (FAMILY_PAD_REGS_SIZE * LPC_FAMILY_NUMBER(gpio_pad) \
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+ (GPIO_REGS_SIZE * LPC_INTERNAL_PAD_NUM(gpio_pad))))
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#define LPC_AD2_MMIO_OFFSET LPC_GPIO_OFFSET(45)
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#define LPC_CLKRUN_MMIO_OFFSET LPC_GPIO_OFFSET(46)
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#define LPC_AD0_MMIO_OFFSET LPC_GPIO_OFFSET(47)
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#define LPC_FRAME_MMIO_OFFSET LPC_GPIO_OFFSET(48)
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#define LPC_AD3_MMIO_OFFSET LPC_GPIO_OFFSET(50)
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#define LPC_AD1_MMIO_OFFSET LPC_GPIO_OFFSET(52)
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/* Value written into pad control reg 0 in early init */
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#define PAD_CFG0_NATIVE(mode, term, inv_rx_tx) (PAD_GPIO_DISABLE \
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| PAD_GPIOFG_HI_Z \
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| PAD_MODE_SELECTION(mode) | PAD_PULL(term))
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#define PAD_CFG0_NATIVE_PU20K(mode) PAD_CFG0_NATIVE(mode, 9, 0) /* PU 20K */
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#define PAD_CFG0_NATIVE_PD20K(mode) PAD_CFG0_NATIVE(mode, 1, 0) /* PD 20K */
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#define PAD_CFG0_NATIVE_M1 PAD_CFG0_NATIVE(1, 0, 0) /* no pull */
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/*
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* Configure value in LPC GPIO PADCFG0 registers. This function would be called
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* to configure for low power/restore LPC GPIO lines
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*/
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static void lpc_gpio_config(u32 cycle)
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{
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if (cycle == SUSPEND_CYCLE) { /* Suspend cycle */
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write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
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LPC_FRAME_MMIO_OFFSET),
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PAD_CFG0_NATIVE_PU20K(1));
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write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
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LPC_AD0_MMIO_OFFSET),
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PAD_CFG0_NATIVE_PU20K(1));
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write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
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LPC_AD1_MMIO_OFFSET),
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PAD_CFG0_NATIVE_PU20K(1));
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write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
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LPC_AD2_MMIO_OFFSET),
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PAD_CFG0_NATIVE_PU20K(1));
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write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
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LPC_AD3_MMIO_OFFSET),
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PAD_CFG0_NATIVE_PU20K(1));
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write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
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LPC_CLKRUN_MMIO_OFFSET),
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PAD_CFG0_NATIVE_PD20K(1));
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} else { /* Resume cycle */
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write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
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LPC_FRAME_MMIO_OFFSET),
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PAD_CFG0_NATIVE_M1);
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write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
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LPC_AD0_MMIO_OFFSET),
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PAD_CFG0_NATIVE_PU20K(1));
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write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
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LPC_AD1_MMIO_OFFSET),
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PAD_CFG0_NATIVE_PU20K(1));
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write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
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LPC_AD2_MMIO_OFFSET),
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PAD_CFG0_NATIVE_PU20K(1));
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write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
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LPC_AD3_MMIO_OFFSET),
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PAD_CFG0_NATIVE_PU20K(1));
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write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
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LPC_CLKRUN_MMIO_OFFSET),
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PAD_CFG0_NATIVE_M1);
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}
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}
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/*
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* configure LPC GPIO lines for low power
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*/
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void lpc_set_low_power(void)
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{
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lpc_gpio_config(SUSPEND_CYCLE);
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}
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/*
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* Configure GPIO lines early during romstage.
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*/
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void lpc_init(void)
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{
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uint16_t pm1_sts;
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uint32_t pm1_cnt;
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int slp_type = 0;
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/*
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* On S3 resume re-initialize GPIO lines which were
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* configured for low power during S3 entry.
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*/
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pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
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pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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if (pm1_sts & WAK_STS)
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slp_type = (pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT;
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if ((slp_type == SLP_TYP_S3) || (slp_type == SLP_TYP_S5))
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lpc_gpio_config(RESUME_CYCLE);
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}
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