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Zheng Bao acd3788bb8 mb/google/skyrim: Expand cbmem console buffer
Expand the size of cbmem console buffer from default value 0x20000 to
0x80000. Verified by running "cbmem -l" in Chromium OS shell.

localhost ~ # cbmem -l
CBMEM table of contents:
    NAME          ID           START      LENGTH
 0. FSP MEMORY  46535052  b97fe000   01000000
 1. CONSOLE     434f4e53  b977e000   00080000
 2. RW MCACHE   574d5346  b977d000   00000360
 3. RO MCACHE   524d5346  b977c000   00000f20
 4. FMAP        464d4150  b977b000   0000047c
 5. TIME STAMP  54494d45  b977a000   00000910
 6. VBOOT WORK  78007343  b9766000   00014000
 7. RAMSTAGE    9a357a9e  b9700000   00066000
 8. ACPI BERT   42455254  b96fc000   00004000
 9. CHROMEOS NVS        434e5653  b96fb000   00000f00
10. REFCODE     04efc0de  b96ab000   00050000
11. MEM INFO    494d454d  b96aa000   00000768
12. RAMOOPS     05430095  b95aa000   00100000
13. COREBOOT    43425442  b95a2000   00008000
14. ACPI        41435049  b957e000   00024000
15. TPM2 TCGLOG 54504d32  b956e000   00010000
16. SMBIOS      534d4254  b9566000   00008000
17. FSP RUNTIME 52505346  ba7febe0   00000004
18. POWER STATE 50535454  ba7feb80   00000060
19. ROMSTAGE    47545352  ba7feb60   00000004
20. EARLY DRAM USAGE    4544524d  ba7feb40   00000008
21. ACPI GNVS   474e5653  ba7feb20   00000020

BUG=246268888
TEST=Skyrim

Change-Id: I79205f31b4cc3276c1c213a171a6bf7e18d73a1c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-10-27 15:46:59 +00:00
3rdparty Update vboot submodule to upstream main 2022-10-27 04:34:25 +00:00
Documentation Docs/releases: Finalize relnotes for the 4.18 release 2022-10-20 20:33:20 +00:00
LICENSES src/mb: Update unlicensable files with the CC-PDDC SPDX ID 2022-08-13 19:25:12 +00:00
configs coreboot_tables: Drop uart PCI addr 2022-10-26 14:12:06 +00:00
payloads payloads/LinuxBoot: Fix Linuxboot kernel fetching for v6.x 2022-10-26 14:12:20 +00:00
spd spd/lp5: Add new memory configuration of H9JCNNNFA5MLYR-N6E 2022-10-20 16:24:06 +00:00
src mb/google/skyrim: Expand cbmem console buffer 2022-10-27 15:46:59 +00:00
tests coreboot_tables: Drop uart PCI addr 2022-10-26 14:12:06 +00:00
util util/cbfstool: Check for metadata hash in verstage 2022-10-26 15:59:58 +00:00
.checkpatch.conf checkpatch.conf: Ignore check for pointer comparisons to NULL 2022-09-22 15:13:35 +00:00
.clang-format
.editorconfig
.gitignore .gitignore: Add .vscode/ 2022-08-30 17:56:55 +00:00
.gitmodules Add SBOM (Software Bill of Materials) Generation 2022-08-22 14:48:46 +00:00
.gitreview
.mailmap
AUTHORS arm/libgcc: Support signed 64-bit division 2022-08-13 17:20:32 +00:00
COPYING
MAINTAINERS MAINTAINERS: Update instructions 2022-10-25 17:03:05 +00:00
Makefile Makefile: Add targets to add and remove symlinks 2022-10-17 14:00:46 +00:00
Makefile.inc util/amdfwtool: Add build rules for amdfwread 2022-10-26 15:56:37 +00:00
README.md Treewide: Remove doxygen config files and targets 2022-05-28 01:24:51 +00:00
gnat.adc
toolchain.inc coreboot: Add support for include-what-you-use 2022-10-11 14:33:28 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.