GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
coreboot-kgpe-d16/src/cpu/intel
History
Sven Schnelle adfbcb79ab MTRR: get physical address size from CPUID 
The current code uses static values for the physical address size
supported by a CPU. This isn't always the right value: I.e. on
model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
Xeons from the same family have 38 bits, which results in invalid
MTRR setup. Fix this by getting the right number from CPUID.

Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/529
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-10 21:51:40 +01:00
..
bga956 Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
car Remove XIP_ROM_BASE 2011-11-01 19:06:23 +01:00
ep80579 MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
hyperthreading Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
microcode Make update-microcodes.sh executable. 2010-10-18 00:20:40 +00:00
model_6bx MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_6dx MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_6ex MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_6fx MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_6xx MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_65x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_67x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_68x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_69x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_106cx MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_1067x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_f0x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_f1x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_f2x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_f3x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_f4x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
slot_1 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. 2011-08-04 08:10:12 +02:00
slot_2 Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. 2010-10-15 07:47:51 +00:00
socket_441 oops. this is weird. CAR addresses should be specified in the socket and not in 2011-01-27 01:11:20 +00:00
socket_FC_PGA370 Get rid of the old romstage-as-bootblock ROM layout 2011-10-28 22:17:36 +02:00
socket_mFCBGA479 Move "select CACHE_AS_RAM" lines from boards into CPU socket. 2010-12-08 08:22:04 +00:00
socket_mFCPGA478 oops. this is weird. CAR addresses should be specified in the socket and not in 2011-01-27 01:11:20 +00:00
socket_mPGA478 Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
socket_mPGA479M Move "select CACHE_AS_RAM" lines from boards into CPU socket. 2010-12-08 08:22:04 +00:00
socket_mPGA603 Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
socket_mPGA604 Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
socket_PGA370 Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. 2010-10-15 07:47:51 +00:00
speedstep ACPI: mark empty get_cst_entries() weak 2012-01-09 11:07:18 +01:00
thermal_monitoring drop unused code (trivial) 2008-08-01 11:53:39 +00:00
Kconfig Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x. 2010-10-13 17:00:42 +00:00
Makefile.inc Create new socket for FCPGA370 and PGA370 CPU's for CAR. Add CAR support for Coppermine FC-PGA CPU's (model_68x). 2010-06-21 19:40:09 +00:00