coreboot-kgpe-d16/src/cpu/x86
Sven Schnelle adfbcb79ab MTRR: get physical address size from CPUID
The current code uses static values for the physical address size
supported by a CPU. This isn't always the right value: I.e. on
model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
Xeons from the same family have 38 bits, which results in invalid
MTRR setup. Fix this by getting the right number from CPUID.

Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/529
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-10 21:51:40 +01:00
..
16bit Remove unused code files and cosmetic changes 2011-11-24 11:43:11 +01:00
32bit Unify use of post_code 2011-04-11 20:17:22 +00:00
cache Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
lapic Bootblock does not need a unique boot_cpu() 2011-12-05 12:20:43 +01:00
mtrr MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
name Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
pae Now that no boards set RAMBASE < 1M, get rid of some dead code. Trivial. 2010-10-20 19:23:22 +00:00
smm SMM: Move wbinvd after pmode jump 2011-10-15 21:16:37 +02:00
tsc Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
fpu_enable.inc Add a few missing license headers based on svn logs, and also add a 2010-09-27 17:53:17 +00:00
Kconfig Remove XIP_ROM_BASE 2011-11-01 19:06:23 +01:00
mmx_disable.inc Add a few missing license headers based on svn logs, and also add a 2010-09-27 17:53:17 +00:00
sse_disable.inc Add a few missing license headers based on svn logs, and also add a 2010-09-27 17:53:17 +00:00
sse_enable.inc Add a few missing license headers based on svn logs, and also add a 2010-09-27 17:53:17 +00:00