9fe20cb381
Samsung SoC files, including Exynos5 (a Cortex-A15
implementation). Since this is an SoC we'll forego the x86-style
{north,south}bridge and cpu distinction. We may try to split some
stuff out before the final version if prudent.
Change-Id: Ie068e9dc3dd836c83d90e282b10d5202e7a4ba9b
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2005
Tested-by: build bot (Jenkins)
32 lines
855 B
Makefile
32 lines
855 B
Makefile
romstage-y += clock.c
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romstage-y += clock_init.c
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romstage-y += exynos_cache.c
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romstage-y += lowlevel_init.S
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romstage-y += lowlevel_init_c.c
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romstage-y += pinmux.c
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romstage-y += power.c
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romstage-y += soc.c
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romstage-y += uart.c
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#ramstage-y += clock.c
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#ramstage-y += clock_init.c
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#ramstage-y += power.c
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#ramstage-y += uart.c
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##ramstage-y += spl.c
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#ramstage-y += pinmux.c
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##ramstage-y += tzpc_init.c
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ramstage-y += clock.c
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ramstage-y += clock_init.c
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ramstage-y += exynos_cache.c
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ramstage-y += lowlevel_init.S
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ramstage-y += lowlevel_init_c.c
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ramstage-y += pinmux.c
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ramstage-y += power.c
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ramstage-y += soc.c
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ramstage-y += uart.c
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#ramstage-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.c
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#ramstage-$(CONFIG_SATA_AHCI) += sata.c
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ramstage-$(CONFIG_SPL_BUILD) += lowlevel_init_c.c
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ramstage-$(CONFIG_SPL_BUILD) += dmc_common.c
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ramstage-$(CONFIG_SPL_BUILD) += dmc_init_ddr3.c
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