coreboot-kgpe-d16/src/mainboard/jetway/pa78vm5
Uwe Hermann ae3f2b3706 Allow selecting the physical USB Debug Port on AMD SB700.
The AMD SB700 allows changing the physical USB port to be used as
USB Debug Port, implement support for this.

Also, fix incorrect PCI device of the SB700 EHCI device. Actually, the
SB700 has _two_ EHCI devices (D18:F2 and D19:F2), but for now we only use
D18:F2. Our generic USBDEBUG code cannot handle multiple EHCI PCI devices
currently, AFAICS.

Hook up all SB700 boards to the CONFIG_USBDEBUG_DEFAULT_PORT facility.

Untested, but should work.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-02 20:36:26 +00:00
..
acpi Commit (non-working!) Jetway PA78VM5 mainboard 2010-08-17 15:19:32 +00:00
acpi_tables.c Commit (non-working!) Jetway PA78VM5 mainboard 2010-08-17 15:19:32 +00:00
chip.h Remove unused mainboard_config definitions. Trivial. 2010-08-26 18:24:04 +00:00
cmos.layout Commit (non-working!) Jetway PA78VM5 mainboard 2010-08-17 15:19:32 +00:00
devicetree.cb Remove unused ide0_enable and sata0_enable entries from SB7xx 2010-09-07 09:18:08 +00:00
dsdt.asl Commit (non-working!) Jetway PA78VM5 mainboard 2010-08-17 15:19:32 +00:00
fadt.c Drop some useless "../../../" in #includes (trivial). 2010-09-25 16:17:20 +00:00
get_bus_conf.c Commit (non-working!) Jetway PA78VM5 mainboard 2010-08-17 15:19:32 +00:00
irq_tables.c Commit (non-working!) Jetway PA78VM5 mainboard 2010-08-17 15:19:32 +00:00
Kconfig Remove redundant HW_MEM_HOLE_SIZEK and HW_MEM_HOLE_SIZE_AUTO_INC settings. 2010-09-28 16:16:58 +00:00
mainboard.c Remove unused mainboard_config definitions. Trivial. 2010-08-26 18:24:04 +00:00
mptable.c Commit (non-working!) Jetway PA78VM5 mainboard 2010-08-17 15:19:32 +00:00
resourcemap.c Commit (non-working!) Jetway PA78VM5 mainboard 2010-08-17 15:19:32 +00:00
romstage.c Allow selecting the physical USB Debug Port on AMD SB700. 2010-10-02 20:36:26 +00:00