ae593879f5
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I22fffa0eab006be2bad4d3dd776b22ad9830faef Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
60 lines
1.5 KiB
C
60 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "chip.h"
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#include <soc/acpi.h>
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#include <soc/pci_devs.h>
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#include <soc/northbridge.h>
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#include <soc/southbridge.h>
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#include <amdblocks/acpimmio.h>
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#include <commonlib/helpers.h>
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static void enable(struct device *dev)
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{
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const struct soc_amd_picasso_config *cfg;
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const struct device *nb_dev = pcidev_path_on_root(GNB_DEVFN);
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struct resource *res;
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uintptr_t bar;
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pci_dev_enable_resources(dev);
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/* Set the proper I2S_PIN_CONFIG state */
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if (!nb_dev || !nb_dev->chip_info)
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return;
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cfg = nb_dev->chip_info;
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res = dev->resource_list;
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if (!res || !res->base) {
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printk(BIOS_ERR, "Error, unable to configure pin in %s\n", __func__);
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return;
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}
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bar = (uintptr_t)res->base;
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write32((void *)(bar + ACP_I2S_PIN_CONFIG), cfg->acp_pin_cfg);
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if (cfg->acp_pin_cfg == I2S_PINS_I2S_TDM)
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sb_clk_output_48Mhz(); /* Internal connection to I2S */
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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static struct device_operations acp_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = enable,
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.ops_pci = &lops_pci,
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};
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static const struct pci_driver acp_driver __pci_driver = {
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.ops = &acp_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICD_ID_AMD_PCO_ACP,
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};
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