6d6d18efe8
Dinar mainboard is an AMD evaluation board for Orochi Platform family15 model 00-0f processor. The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets. 16 cores InterLagos Opteron processor are supported. Windows 7 are verified on this platform. Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/564 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
104 lines
3.8 KiB
Text
104 lines
3.8 KiB
Text
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2012 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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#
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chip northbridge/amd/agesa/family15/root_complex
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device lapic_cluster 0 on
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chip cpu/amd/agesa/family15
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device lapic 0x20 on end
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end
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end
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device pci_domain 0 on
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subsystemid 0x1022 0x1705 inherit
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chip northbridge/amd/agesa/family15 # CPU side of HT root complex
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device pci 18.0 on end # Link 0
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device pci 18.0 on # Link 1, IO-HUB on socket0 link 2(internal Node0 Link 1)
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chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex
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device pci 0.0 on end # HT Root Complex
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device pci 0.1 off end # CLKCONFIG
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device pci 2.0 on end # GPP1 Port0
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device pci 3.0 off end # GPP1 Port1
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device pci 4.0 off end # GPP3a Port0
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device pci 5.0 off end # GPP3a Port1
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device pci 6.0 off end # GPP3a Port2
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device pci 7.0 off end # GPP3a Port3
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device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
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device pci 9.0 off end # GPP3a Port4
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device pci a.0 off end # GPP3a Port5
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device pci b.0 off end # GPP2 Port0 (Not for sr5650)
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device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
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device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
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register "gpp1_configuration" = "0" # Configuration 16:0 default
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register "gpp2_configuration" = "1" # Configuration 8:8
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register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
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register "port_enable" = "0x2104"
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end # northbridge/amd/cimx/rd890
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chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pri bus
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device pci 11.0 on end # SATA
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device pci 12.0 on end # USB1
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device pci 12.1 on end # USB1
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device pci 12.2 on end # USB1
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device pci 13.0 on end # USB2
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device pci 13.1 on end # USB2
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device pci 13.2 on end # USB2
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device pci 14.0 on # SM
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end # SM
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device pci 14.1 off end # IDE 0x439c
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device pci 14.2 off end # HDA 0x4383
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device pci 14.3 on # LPC
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chip superio/smsc/sch4037 # SIO SMSC SCH4037
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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irq 0x74 = 2
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end
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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irq 0x74 = 4
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end
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device pnp 2e.4 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.5 on # COM2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.7 on # PS/2 keyboard / mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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end #SIO SMSC307
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end #LPC
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device pci 14.4 on end # PCI bridge, 0x4384
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device pci 14.5 on end # USB 3
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register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE
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end #southbridge/amd/cimx/sb700
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end # device pci 18.0
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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device pci 18.4 on end
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device pci 18.5 on end
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end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex
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end #pci_domain
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end #northbridge/amd/agesa/family15/root_complex
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