266a1f794d
Instead of hardcoding the PCI mmio size read it from devicetree. Set a default value of 2048 MiB and 1024MiB for laptops without discrete graphics. Tested on Sandybridge Lenovo T520. Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
120 lines
3.5 KiB
Text
120 lines
3.5 KiB
Text
chip northbridge/intel/sandybridge
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register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }"
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register "gfx.link_frequency_270_mhz" = "0"
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register "gfx.ndid" = "2"
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register "gfx.use_spread_spectrum_clock" = "1"
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register "gpu_cpu_backlight" = "0x00001312"
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register "gpu_dp_b_hotplug" = "4"
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register "gpu_dp_c_hotplug" = "4"
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register "gpu_dp_d_hotplug" = "4"
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register "gpu_panel_port_select" = "1"
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register "gpu_panel_power_backlight_off_delay" = "2000"
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register "gpu_panel_power_backlight_on_delay" = "10"
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register "gpu_panel_power_cycle_delay" = "6"
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register "gpu_panel_power_down_delay" = "500"
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register "gpu_panel_power_up_delay" = "2000"
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register "gpu_pch_backlight" = "0x13121312"
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device cpu_cluster 0x0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0x0 on
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end
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end
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chip cpu/intel/model_206ax
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register "c1_acpower" = "1"
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register "c1_battery" = "1"
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register "c2_acpower" = "3"
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register "c2_battery" = "3"
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register "c3_acpower" = "5"
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register "c3_battery" = "5"
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device lapic 0xacac off
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end
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end
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end
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register "pci_mmio_size" = "2048"
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device domain 0x0 on
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "docking_supported" = "0"
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register "gen1_dec" = "0x000c0681"
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register "gen2_dec" = "0x000c1641"
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register "gen3_dec" = "0x001c0301"
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register "gen4_dec" = "0x00fc0701"
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register "gpi7_routing" = "2"
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register "p_cnt_throttling_supported" = "1"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x1"
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device pci 16.0 on # Management Engine Interface 1
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subsystemid 0x8086 0x7270
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end
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device pci 16.1 off # Management Engine Interface 2
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end
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device pci 16.2 off # Management Engine IDE-R
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end
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device pci 16.3 off # Management Engine KT
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end
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device pci 19.0 off # Intel Gigabit Ethernet
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end
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device pci 1a.0 on # USB2 EHCI #2 Unsupported PCI device 8086:1c2c
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subsystemid 0x8086 0x7270
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end
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device pci 1b.0 on # High Definition Audio Audio controller
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subsystemid 0x8086 0x7270
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end
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device pci 1c.0 on # PCIe Port #1
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subsystemid 0x8086 0x7270
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end
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device pci 1c.1 on # PCIe Port #2
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subsystemid 0x8086 0x7270
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end
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device pci 1c.2 off # PCIe Port #3
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end
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device pci 1c.3 off # PCIe Port #4
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end
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device pci 1c.4 off # PCIe Port #5
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end
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device pci 1c.5 off # PCIe Port #6
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end
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device pci 1c.6 off # PCIe Port #7
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end
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device pci 1c.7 off # PCIe Port #8
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end
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device pci 1d.0 on # USB2 EHCI #1 Unsupported PCI device 8086:1c27
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subsystemid 0x8086 0x7270
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end
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device pci 1e.0 off # PCI bridge
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end
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device pci 1f.0 on # LPC bridge PCI-LPC bridge
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subsystemid 0x8086 0x7270
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end
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device pci 1f.2 on # SATA Controller 1
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subsystemid 0x8086 0x7270
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end
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device pci 1f.3 on # SMBus
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subsystemid 0x8086 0x7270
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end
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device pci 1f.5 off # SATA Controller 2
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end
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device pci 1f.6 off # Thermal
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end
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end
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device pci 00.0 on # Host bridge Host bridge
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subsystemid 0x106b 0x00eb
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end
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device pci 01.0 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0101
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subsystemid 0x106b 0x00eb
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end
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device pci 02.0 on # Internal graphics VGA controller
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subsystemid 0x106b 0x00eb
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end
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device pci 1a.7 on
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subsystemid 0x8086 0x7270
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end
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device pci 1d.7 on
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subsystemid 0x8086 0x7270
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end
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end
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end
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