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Aamir Bohra af343cff76 soc/amd/picasso: Allow end range entry for max device ID in IVRS
Allow hot plug devices to subscribe to IOMMU services. Currently the
IOMMU end range is limited to device B:0 D:1f F:6. This prevents the
devices on bus 1 and higher to subscribe to IOMMU services. As per AMD
IOMMU spec v3 section 5.2.2.1 all possible device IDs must be defined,
whether the device ID is actually populated or not. Device entries are
used to report ranges when hot-plug and SR-IOV devices are possible.
With this change the hot plug devices can now bind to IOMMU services
(as tested on kernel v5.4), and below errors are not seen in dmesg.

AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.3 domain=0x0000]

AMD-Vi: Event logged [IO_PAGE_FAULT device=05:00.0 domain=0x0000]

AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.4 domain=0x0000]

TEST= Verify dGPU can enumerate on hotplug. No IO page fault errors seen.
      The hot plug devices can successfully bind to IOMMU services in
      kernel.

Signed-off-by: Aamir Bohra <aamirbohra@gmail.com>
Change-Id: I256c0f8032662674a4d75746de49c250e341c579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55816
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-06 22:10:10 +00:00
3rdparty Update vboot submodule to upstream main 2021-07-01 09:38:12 +00:00
Documentation src: Consolidate x86_64 support Kconfig 2021-07-02 08:19:21 +00:00
LICENSES treewide: Remove trailing whitespace 2021-02-17 17:30:05 +00:00
configs configs/config.foxconn_g41m: Build test with X86_64 2021-07-06 06:11:50 +00:00
payloads nvs: Add Chrome OS NVS (CNVS) information to coreboot tables 2021-06-18 18:38:14 +00:00
src soc/amd/picasso: Allow end range entry for max device ID in IVRS 2021-07-06 22:10:10 +00:00
tests helpers: Introduce retry macro 2021-06-26 10:09:06 +00:00
util util/board_status: Do not display grep message 2021-07-05 10:51:12 +00:00
.checkpatch.conf lint: checkpatch: Only exclude specific src/vendorcode/ subdirectories 2021-04-06 16:04:41 +00:00
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.editorconfig Add .editorconfig file 2019-09-10 12:52:18 +00:00
.gitignore .gitignore: Ignore .test/.dependencies globally 2020-10-31 18:21:36 +00:00
.gitmodules .gitmodules: Update intel-microcode submodule to track branch=main 2021-06-09 17:20:50 +00:00
.gitreview
AUTHORS AUTHORS, util/: Drop individual copyright notices 2020-05-09 21:21:32 +00:00
COPYING
MAINTAINERS Revert "src/mainboard: Add Star Labs labtop series" 2021-06-04 18:52:32 +00:00
Makefile tests: improve code coverage support 2021-05-19 19:56:02 +00:00
Makefile.inc option: Introduce `CMOS_LAYOUT_FILE` Kconfig symbol 2021-05-18 11:43:49 +00:00
README.md README.md: Remove link to deprecated wiki 2019-11-16 20:39:55 +00:00
gnat.adc treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
toolchain.inc toolchain.inc: copy architecture specific CFLAGS to GCC_ADAFLAGS 2021-07-01 09:43:54 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.