Angel Pons afc6c0ae12 mb/google/slippy: Correct memory-down SPD handling ... MRC only uses the SPD data for the first index, and ignores the rest. Moreover, index 1 corresponds to the second DIMM on the first channel, which does not exist on ULT (only one DIMM per channel is supported). Copy the SPD to the first DIMM on channel 1 instead. Adjust northbridge code to retrieve the serial number from the correct SPD data block. Tested on Google Wolf, both channels are still correctly detected. Change-Id: Ic60ff75043e6b96a59baa9e5ebffb712a100a934 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2021-03-19 11:19:51 +00:00
..
acpi
arch	cbfs: Remove prog_locate() for payloads (SELF and FIT)	2021-03-17 00:13:53 +00:00
commonlib	cbfs: Move stage header into a CBFS attribute	2021-03-17 08:10:00 +00:00
console
cpu	cpu/x86/mp_init.c: Calculate perm_smbase from ramstage data	2021-03-18 08:14:32 +00:00
device	pciexp_device: Rewrite LTR configuration	2021-03-15 06:04:38 +00:00
drivers	cbfs: Replace more instances of cbfs_boot_locate() with newer APIs	2021-03-17 08:10:20 +00:00
ec
include	cpu/x86/smm: Move apic_id_to_cpu map to smm_stub params	2021-03-18 08:13:33 +00:00
lib	spd_bin: Replace get_spd_cbfs_rdev() with spd_cbfs_map()	2021-03-17 08:10:35 +00:00
mainboard	mb/google/slippy: Correct memory-down SPD handling	2021-03-19 11:19:51 +00:00
northbridge	mb/google/slippy: Correct memory-down SPD handling	2021-03-19 11:19:51 +00:00
security	cbfs: Replace more instances of cbfs_boot_locate() with newer APIs	2021-03-17 08:10:20 +00:00
soc	soc/amd/common: Make fch_spi_config_modes static	2021-03-18 17:19:06 +00:00
southbridge
superio
vendorcode	vc/google/chromeos/acpi: Add type to OIPG declaration	2021-03-18 18:10:35 +00:00
Kconfig