a7c92a6dc4
I think that since the directory specifies the architecture and the board, it is redundant information to name it something else, and it makes it more difficult to automate the build process (buildrom). Signed-off-by: Myles Watson <myles@pel.cs.byu.edu> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3090 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
34 lines
925 B
Text
34 lines
925 B
Text
# Config file for the ThinCan dbe61
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target dbe61
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mainboard artecgroup/dbe61
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# HACK to get the right TSC support.
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option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
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option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
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option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
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## ROM_SIZE is the total number of bytes allocated for coreboot use
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## (normal AND fallback images and payloads).
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## leave 36k for vsa and 32K for video ROM
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#option ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024
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#No VGA for now
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option ROM_SIZE = 1024*512 - 36*1024
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# ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
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## not including any payload.
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option ROM_IMAGE_SIZE=64*1024
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option FALLBACK_SIZE = ROM_SIZE
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option DEFAULT_CONSOLE_LOGLEVEL = 11
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option MAXIMUM_CONSOLE_LOGLEVEL = 11
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romimage "fallback"
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option USE_FALLBACK_IMAGE=1
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option COREBOOT_EXTRA_VERSION=".0Fallback"
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payload ../payload.elf
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end
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buildrom ./coreboot.rom ROM_SIZE "fallback"
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