a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
78 lines
2.3 KiB
C
78 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2004 Ronald G. Minnich
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include "i82801dx.h"
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typedef struct southbridge_intel_i82801dx_config config_t;
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static void ide_init(struct device *dev)
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{
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/* Get the chip configuration */
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config_t *config = dev->chip_info;
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/* Enable IDE devices so the Linux IDE driver will work. */
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uint16_t ideTimingConfig;
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ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
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ideTimingConfig &= ~IDE_DECODE_ENABLE;
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if (!config || config->ide0_enable) {
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/* Enable primary IDE interface. */
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ideTimingConfig |= IDE_DECODE_ENABLE;
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printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n");
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} else {
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printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n");
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}
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pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
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ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
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ideTimingConfig &= ~IDE_DECODE_ENABLE;
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if (!config || config->ide1_enable) {
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/* Enable secondary IDE interface. */
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ideTimingConfig |= IDE_DECODE_ENABLE;
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printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n");
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} else {
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printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n");
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}
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pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
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}
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static struct device_operations ide_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ide_init,
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.scan_bus = 0,
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.enable = i82801dx_enable,
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};
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/* 82801DB */
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static const struct pci_driver i82801db_ide __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x24cb,
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};
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/* 82801DBM */
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static const struct pci_driver i82801dbm_ide __pci_driver = {
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.ops = &ide_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = 0x24ca,
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};
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