Elyes HAOUAS b12ece98b0 src/{include,arch,cpu,lib}: Add missing 'include <types.h>' ... <types.h> is supposed to provide <stdint.h> and <stddef.h>. So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: I57aead27806e307b9827fc7ee2cd663f12ee6e5e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>		2019-05-29 20:27:18 +00:00
..
acpi
arch	src/{include,arch,cpu,lib}: Add missing 'include <types.h>'	2019-05-29 20:27:18 +00:00
commonlib	commonlib: fix typo LB_TAB_* (instead of LB_TAG_*)	2019-05-29 20:12:57 +00:00
console	console: Move poor-man's atoi() into string.h	2019-05-23 08:43:12 +00:00
cpu	src/{include,arch,cpu,lib}: Add missing 'include <types.h>'	2019-05-29 20:27:18 +00:00
device	vboot: remove OPROM-related code	2019-05-15 17:50:08 +00:00
drivers	soc/intel/skylake: Use common cpu/intel/car romstage code	2019-05-29 20:18:43 +00:00
ec	ec/google/wilco: Fix radio control command	2019-05-24 16:43:57 +00:00
include	src/{include,arch,cpu,lib}: Add missing 'include <types.h>'	2019-05-29 20:27:18 +00:00
lib	src/{include,arch,cpu,lib}: Add missing 'include <types.h>'	2019-05-29 20:27:18 +00:00
mainboard	drivers/intel/fsp1.1: Simplify bootflow and clean up	2019-05-29 20:17:48 +00:00
northbridge	intel/sandybridge: Make timC training more robust.	2019-05-29 20:02:40 +00:00
security	post_code: add post code for failure to load next stage	2019-05-22 14:21:57 +00:00
soc	soc/intel/denverton_ns: Don't use CONFIG_CBFS_SIZE	2019-05-29 20:24:13 +00:00
southbridge	sb/intel/*: Delete early_spi	2019-05-29 20:08:31 +00:00
superio	superio/fintek/f71863fg: Remove variable set but not used	2019-05-25 18:20:15 +00:00
vendorcode	AGESA binaryPI: Add AGESA entry timestamps	2019-05-25 08:39:05 +00:00
Kconfig	src/Kconfig: Move DRAM section to src/lib/Kconfig	2019-05-20 10:58:56 +00:00