b1fa25fab7
Move some of the common memory code that was being performed in mainboard into the soc to reduce redundant code going forward. BUG=b:145642089 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel and verify memory size shows 8GB. Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
60 lines
1.4 KiB
Makefile
60 lines
1.4 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_TIGERLAKE_BASE),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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# all (bootblock, verstage, romstage, postcar, ramstage)
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all-y += gspi.c
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all-y += i2c.c
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all-y += pmutil.c
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all-y += spi.c
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all-y += uart.c
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/cpu.c
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bootblock-y += bootblock/pch.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += espi.c
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bootblock-y += gpio.c
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bootblock-y += p2sb.c
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romstage-y += espi.c
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romstage-y += gpio.c
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romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += meminit_tgl.c
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romstage-y += reset.c
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ramstage-y += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += elog.c
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ramstage-y += espi.c
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ramstage-y += finalize.c
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ramstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += fsp_params_tgl.c
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ramstage-$(CONFIG_SOC_INTEL_JASPERLAKE) += fsp_params_jsl.c
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ramstage-y += gpio.c
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ramstage-y += graphics.c
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ramstage-y += lockdown.c
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ramstage-y += p2sb.c
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ramstage-y += pmc.c
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ramstage-y += reset.c
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ramstage-y += smmrelocate.c
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ramstage-y += systemagent.c
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ramstage-y += sd.c
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smm-y += gpio.c
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smm-y += p2sb.c
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smm-y += pmc.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += uart.c
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CPPFLAGS_common += -I$(src)/soc/intel/tigerlake
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CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include
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endif
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