6a2ece7bd1
Move code that gets used in stages other than ramstage to pmutil.c and only build pmc.c in ramstage. This is done for consistency with other platforms. Change-Id: Iefb4fc86f3995ee6f259b7b287e04f7f94d8d025 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
61 lines
1.6 KiB
C
61 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <intelblocks/pmc.h>
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#include <intelblocks/pmclib.h>
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#include <intelblocks/rtc.h>
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#include <reg_script.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include "chip.h"
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/* Fill up PMC resource structure */
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int pmc_soc_get_resources(struct pmc_resource_config *cfg)
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{
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cfg->pwrmbase_offset = PWRMBASE;
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cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS;
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cfg->pwrmbase_size = PCH_PWRM_BASE_SIZE;
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cfg->abase_offset = ABASE;
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cfg->abase_addr = ACPI_BASE_ADDRESS;
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cfg->abase_size = ACPI_BASE_SIZE;
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return 0;
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}
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static const struct reg_script pch_pmc_misc_init_script[] = {
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/* Enable SCI and clear SLP requests. */
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REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
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REG_SCRIPT_END
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};
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static const struct reg_script pmc_write1_to_clear_script[] = {
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REG_PCI_OR32(GEN_PMCON_A, 0),
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REG_PCI_OR32(GEN_PMCON_B, 0),
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REG_PCI_OR32(GEN_PMCON_B, 0),
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REG_RES_OR32(PWRMBASE, GBLRST_CAUSE0, 0),
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REG_RES_OR32(PWRMBASE, GBLRST_CAUSE1, 0),
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REG_SCRIPT_END
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};
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void pmc_soc_init(struct device *dev)
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{
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pmc_set_power_failure_state(true);
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pmc_gpe_init();
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/* Note that certain bits may be cleared from running script as
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* certain bit fields are write 1 to clear. */
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reg_script_run_on_dev(dev, pch_pmc_misc_init_script);
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pmc_set_acpi_mode();
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/* Clear registers that contain write-1-to-clear bits. */
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reg_script_run_on_dev(dev, pmc_write1_to_clear_script);
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}
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void pmc_lock_smi(void)
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{
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printk(BIOS_DEBUG, "Locking SMM enable.\n");
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pci_or_config32(PCH_DEV_PMC, GEN_PMCON_A, SMI_LOCK);
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}
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