fd14d4414a
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
304 lines
7.4 KiB
C
304 lines
7.4 KiB
C
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/* ***************************************************************************/
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/* **/
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/* * BIST */
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/* **/
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/* * GX2 BISTs need to be run before BTB or caches are enabled.*/
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/* * BIST result left in registers on failure to be checked with FS2.*/
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/* **/
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/* ***************************************************************************/
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static void
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BIST(void){
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int msrnum;
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msr_t msr;
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/* DM*/
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msrnum = CPU_DM_CONFIG0;
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msr = rdmsr(msrnum);
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msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
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wrmsr(msrnum, msr);
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msr.lo = 0x00000003F;
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msr.hi = 0x000000000;
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msrnum = CPU_DM_BIST;
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wrmsr(msrnum, msr);
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outb(POST_CPU_DM_BIST_FAILURE, 0x80); /* 0x29*/
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msr = rdmsr(msrnum); /* read back for pass fail*/
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msr.lo &= 0x0F3FF0000;
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if (msr.lo != 0xfeff0000)
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goto BISTFail;
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msrnum = CPU_DM_CONFIG0;
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msr = rdmsr(msrnum);
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msr.lo &= ~ DM_CONFIG0_LOWER_DCDIS_SET;
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wrmsr(msrnum, msr);
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/* FPU*/
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msr.lo = 0x000000131;
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msr.hi = 0;
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msrnum = CPU_FP_UROM_BIST;
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wrmsr(msrnum, msr);
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outb(POST_CPU_FPU_BIST_FAILURE, 0x80); /* 0x89*/
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inb(0x80); /* IO delay*/
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msr = rdmsr(msrnum); /* read back for pass fail*/
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while ((msr.lo&0x884) != 0x884)
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msr = rdmsr(msrnum); /* Endless loop if BIST is broken*/
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if ((msr.lo&0x642) != 0x642)
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goto BISTFail;
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msr.lo = msr.hi = 0; /* clear FPU BIST bits*/
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msrnum = CPU_FP_UROM_BIST;
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wrmsr(msrnum, msr);
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/* BTB*/
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msr.lo = 0x000000303;
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msr.hi = 0x000000000;
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msrnum = CPU_PF_BTBRMA_BIST;
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wrmsr(msrnum, msr);
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outb(POST_CPU_BTB_BIST_FAILURE , 0x80); /* 0x8A*/
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msr = rdmsr(msrnum); /* read back for pass fail*/
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if ((msr.lo & 0x3030) != 0x3030)
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goto BISTFail;
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return;
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BISTFail:
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print_err("BIST failed!\n");
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while(1);
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}
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/* ***************************************************************************/
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/* * cpuRegInit*/
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/* ***************************************************************************/
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void
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cpuRegInit (void){
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int msrnum;
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msr_t msr;
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/* Turn on BTM for early debug based on setup. */
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/*if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {*/
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/*
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* The following is only for diagnostics mode; do not use for OLPC
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*/
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if (0) {
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/* Set Diagnostic Mode */
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msrnum = CPU_GLD_MSR_DIAG;
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msr.hi = 0;
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msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
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wrmsr(msrnum, msr);
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/* Set up GLCP to grab BTM data.*/
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msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/
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msr.hi = 0x0;
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msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/
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wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/
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/* ;Turn off debug clock*/
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msrnum = 0x04C000016; /* DBG_CLK_CTL*/
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msr.lo = 0x00; /* No clock*/
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msr.hi = 0x00;
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wrmsr(msrnum, msr);
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/* ;Set debug clock to CPU*/
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msrnum = 0x04C000016; /* DBG_CLK_CTL*/
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msr.lo = 0x01; /* CPU CLOCK*/
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msr.hi = 0x00;
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wrmsr(msrnum, msr);
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/* ;Set fifo ctl to BTM bits wide*/
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msrnum = 0x04C00005E; /* FIFO_CTL*/
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msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/
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wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/
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/* Bit [19] sets it up in slow data mode.*/
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/* ;enable fifo loading - BTM sizing will constrain*/
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/* ; only valid BTM packets to load - this action should always be on*/
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msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/
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msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/
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msr.hi = 0x000000000; /* */
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wrmsr(msrnum, msr);
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/* ;start storing diag data in the fifo*/
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msrnum = 0x04C00005F; /* DIAG CTL*/
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msr.lo = 0x080000000; /* enable actions*/
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msr.hi = 0x000000000;
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wrmsr(msrnum, msr);
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/* Set up delay on data lines, so that the hold time*/
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/* is 1 ns.*/
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msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/
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msr.lo = 0x082b5ad68;
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msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/
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wrmsr(msrnum, msr);
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/* Set up DF to output diag information on DF pins.*/
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msrnum = DF_GLD_MSR_MASTER_CONF;
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msr.lo = 0x0220;
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msr.hi = 0;
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wrmsr(msrnum, msr);
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msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/
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msr.hi = 0x0;
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msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/
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wrmsr(msrnum, msr);
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/* end of code for BTM */
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}
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/* Enable Suspend on Halt*/
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msrnum = CPU_XC_CONFIG;
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msr = rdmsr(msrnum);
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msr.lo |= XC_CONFIG_SUSP_ON_HLT;
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wrmsr(msrnum, msr);
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/* ENable SUSP and allow TSC to run in Suspend */
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/* to keep speed detection happy*/
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msrnum = CPU_BC_CONF_0;
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msr = rdmsr(msrnum);
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msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
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wrmsr(msrnum, msr);
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/* Setup throttling to proper mode if it is ever enabled.*/
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msrnum = 0x04C00001E;
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msr.hi = 0x000000000;
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msr.lo = 0x00000603C;
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wrmsr(msrnum, msr);
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/* Only do this if we are building for 5535*/
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/* */
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/* FooGlue Setup*/
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/* */
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#if 1
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/* Enable CIS mode B in FooGlue*/
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msrnum = MSR_FG + 0x10;
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msr = rdmsr(msrnum);
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msr.lo &= ~3;
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msr.lo |= 2; /* ModeB*/
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wrmsr(msrnum, msr);
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#endif
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/* */
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/* Disable DOT PLL. Graphics init will enable it if needed.*/
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/* */
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msrnum = GLCP_DOTPLL;
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msr = rdmsr(msrnum);
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msr.lo |= DOTPPL_LOWER_PD_SET;
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wrmsr(msrnum, msr);
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/* */
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/* Enable RSDC*/
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/* */
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msrnum = 0x1301 ;
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msr = rdmsr(msrnum);
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msr.lo |= 0x08;
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wrmsr(msrnum, msr);
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/* */
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/* BIST*/
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/* */
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/*if (getnvram( TOKEN_BIST_ENABLE) & == TVALUE_DISABLE) {*/
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{
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// BIST();
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}
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/* */
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/* Enable BTB*/
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/* */
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/* I hate to put this check here but it doesn't really work in cpubug.asm*/
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msrnum = MSR_GLCP+0x17;
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msr = rdmsr(msrnum);
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if (msr.lo >= CPU_REV_2_1){
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msrnum = CPU_PF_BTB_CONF;
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msr = rdmsr(msrnum);
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msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET;
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wrmsr(msrnum, msr);
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}
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/* */
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/* FPU impercise exceptions bit*/
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/* */
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/*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/
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{
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msrnum = CPU_FPU_MSR_MODE;
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msr = rdmsr(msrnum);
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msr.lo |= FPU_IE_SET;
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wrmsr(msrnum, msr);
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}
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#if 0
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/* */
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/* Cache Overides*/
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/* */
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/* This code disables the data cache. Don't execute this
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* unless you're testing something.
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*/
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/* Allow NVRam to override DM Setup*/
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/*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/
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{
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msrnum = CPU_DM_CONFIG0;
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msr = rdmsr(msrnum);
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msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET;
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wrmsr(msrnum, msr);
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}
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/* This code disables the instruction cache. Don't execute
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* this unless you're testing something.
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*/
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/* Allow NVRam to override IM Setup*/
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/*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/
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{
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msrnum = CPU_IM_CONFIG;
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msr = rdmsr(msrnum);
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msr.lo |= IM_CONFIG_LOWER_ICD_SET;
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wrmsr(msrnum, msr);
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}
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#endif
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}
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/* ***************************************************************************/
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/* **/
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/* * MTestPinCheckBX*/
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/* **/
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/* * Set MTEST pins to expected values from OPTIONS.INC/NVRAM*/
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/* * This version is called when there isn't a stack available*/
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/* **/
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/* ***************************************************************************/
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static void
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MTestPinCheckBX (void){
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int msrnum;
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msr_t msr;
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/*if (getnvram( TOKEN_MTEST_ENABLE) ==TVALUE_DISABLE ) {*/
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/* return ; */
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/* } */
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/* Turn on MTEST*/
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msrnum = MC_CFCLK_DBUG;
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msr = rdmsr(msrnum);
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msr.hi |= CFCLK_UPPER_MTST_B2B_DIS_SET | CFCLK_UPPER_MTEST_EN_SET;
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wrmsr(msrnum, msr);
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msrnum = GLCP_SYS_RSTPLL /* Get SDR/DDR mode from GLCP*/;
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msr = rdmsr(msrnum);
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msr.lo >>= RSTPPL_LOWER_SDRMODE_SHIFT;
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if (msr.lo & 1) {
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msrnum = MC_CFCLK_DBUG; /* Turn on SDR MTEST stuff*/
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msr = rdmsr(msrnum);
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msr.lo |= CFCLK_LOWER_SDCLK_SET;
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msr.hi |= CFCLK_UPPER_MTST_DQS_EN_SET;
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wrmsr(msrnum, msr);
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}
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/* Lock the cache down here.*/
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__asm__("wbinvd\n");
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}
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