cfa435a0ff
If the VTd feature is enabled, there will be up to two fixed resources which are set up by the FSP. Add these resources to the list of system resources so that the PCI enumerator will know them. Change-Id: If96fc1c93746e3c7f510e5b3095ea3090e1b8807 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/30991 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
107 lines
3.1 KiB
C
107 lines
3.1 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Intel Corp.
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* (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
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* (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
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* Copyright (C) 2019 Siemens AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/cpu.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <fsp/util.h>
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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#include <soc/systemagent.h>
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/*
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* SoC implementation
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*
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* Add all known fixed memory ranges for Host Controller/Memory
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* controller.
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*/
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
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"PCIEXBAR" },
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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};
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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ARRAY_SIZE(soc_fixed_resources));
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/* Add VTd resources if VTd is enabled. These resources were
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set up by the FSP-S call. */
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if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
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return;
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if (MCHBAR32(GFXVTBAR) & VTBAR_ENABLED) {
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mmio_resource(dev, *index,
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(MCHBAR64(GFXVTBAR) & VTBAR_MASK) / KiB,
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VTBAR_SIZE / KiB);
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(*index)++;
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}
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if (MCHBAR32(DEFVTBAR) & VTBAR_ENABLED) {
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mmio_resource(dev, *index,
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(MCHBAR64(DEFVTBAR) & VTBAR_MASK) / KiB,
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VTBAR_SIZE / KiB);
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(*index)++;
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}
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}
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int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
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uint64_t *prmrr_mask)
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{
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const void *hob;
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size_t hob_size, prmrr_size;
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uint64_t phys_address_mask;
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const uint8_t prmrr_phys_base_guid[16] = {
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0x38, 0x3a, 0x81, 0x9f, 0xb0, 0x6f, 0xa7, 0x4f,
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0xaf, 0x79, 0x8a, 0x4e, 0x74, 0xdd, 0x48, 0x33
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};
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const uint8_t prmrr_size_guid[16] = {
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0x44, 0xed, 0x0b, 0x99, 0x4e, 0x9b, 0x26, 0x42,
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0xa5, 0x97, 0x28, 0x36, 0x76, 0x6b, 0x5c, 0x41
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};
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hob = fsp_find_extension_hob_by_guid(prmrr_phys_base_guid,
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&hob_size);
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if (!hob) {
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printk(BIOS_ERR, "Failed to locate PRMRR base hob\n");
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return -1;
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}
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if (hob_size != sizeof(uint64_t)) {
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printk(BIOS_ERR, "Incorrect PRMRR base hob size\n");
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return -1;
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}
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*prmrr_base = *(uint64_t *) hob;
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hob = fsp_find_extension_hob_by_guid(prmrr_size_guid,
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&hob_size);
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if (!hob) {
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printk(BIOS_ERR, "Failed to locate PRMRR size hob\n");
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return -1;
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}
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if (hob_size != sizeof(uint64_t)) {
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printk(BIOS_ERR, "Incorrect PRMRR base hob size\n");
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return -1;
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}
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prmrr_size = *(uint64_t *) hob;
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phys_address_mask = (1ULL << cpu_phys_address_size()) - 1;
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*prmrr_mask = phys_address_mask & ~(uint64_t)(prmrr_size - 1);
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return 0;
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}
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