Subrata Banik c204aaa23b soc/intel/skylake: Add LPC and SPI lock down config option ... This patch to provide new config options to perform LPC and SPI lock down either by FSP or coreboot. Remove EISS bit programming as well. TEST=Build and boot Eve and Poppy. Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2017-08-25 17:58:08 +00:00
..
acpi	*.asl: Remove obsolete reference to TPM ASL file	2017-04-24 19:14:11 +02:00
spd
acpi_tables.c
board_info.txt
boardid.c
bootblock_mainboard.c
chromeos.c	vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by default	2017-03-28 22:15:46 +02:00
chromeos.fmd
cmos.layout
devicetree.cb	soc/intel/skylake: Add LPC and SPI lock down config option	2017-08-25 17:58:08 +00:00
dsdt.asl
ec.c
ec.h	mainboards: Remove unused EC event for thermal overload	2017-07-01 02:47:30 +00:00
gpio.h
Kconfig	mainboard/*/*/Kconfig: Remove MONOTONIC_TIMER_MSR selection	2017-06-02 16:45:28 +02:00
Kconfig.name
mainboard.c
Makefile.inc
pei_data.c
ramstage.c
romstage.c
romstage_fsp20.c
smihandler.c