967058f807
The SPI drivers for tegra and exynos5420 have code in them which waits for a frame header and leaves filler data out. The SPI driver shouldn't have support for frame headers directly. If a device uses them, it should support them itself. That makes the SPI drivers simpler and easier to write. When moving the frame handling logic into the EC support code, EC communication continued to work on tegra but no longer worked on exynos5420. That suggested the SPI driver on the 5420 wasn't working correctly, so I replaced that with the implementation in depthcharge. Unfortunately that implementation doesn't support waiting for a frame header for the EC, so these changes are combined into one. BUG=None TEST=Built and booted on pit. Built and booted on nyan. In both cases, verified that there were no error messages from the SPI drivers or the EC code. BRANCH=None Original-Change-Id: I62a68820c632f154acece94f54276ddcd1442c09 Original-Signed-off-by: Gabe Black <gabeblack@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/191192 Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Gabe Black <gabeblack@chromium.org> Original-Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4fcfed280ad70f14a013d5353aa0bee0af540630) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id8824523abc7afcbc214845901628833e135d142 Reviewed-on: http://review.coreboot.org/7706 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
72 lines
2.1 KiB
C
72 lines
2.1 KiB
C
/*
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __NVIDIA_TEGRA124_SPI_H__
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#define __NVIDIA_TEGRA124_SPI_H__
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#include <spi-generic.h>
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#include <stddef.h>
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#include "dma.h"
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struct tegra_spi_regs {
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u32 command1; /* 0x000: SPI_COMMAND1 */
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u32 command2; /* 0x004: SPI_COMMAND2 */
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u32 timing1; /* 0x008: SPI_CS_TIM1 */
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u32 timing2; /* 0x00c: SPI_CS_TIM2 */
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u32 trans_status; /* 0x010: SPI_TRANS_STATUS */
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u32 fifo_status; /* 0x014: SPI_FIFO_STATUS */
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u32 tx_data; /* 0x018: SPI_TX_DATA */
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u32 rx_data; /* 0x01c: SPI_RX_DATA */
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u32 dma_ctl; /* 0x020: SPI_DMA_CTL */
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u32 dma_blk; /* 0x024: SPI_DMA_BLK */
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u32 rsvd[56]; /* 0x028-0x107: reserved */
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u32 tx_fifo; /* 0x108: SPI_FIFO1 */
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u32 rsvd2[31]; /* 0x10c-0x187 reserved */
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u32 rx_fifo; /* 0x188: SPI_FIFO2 */
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u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */
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} __attribute__((packed));
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check_member(tegra_spi_regs, spare_ctl, 0x18c);
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enum spi_xfer_mode {
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XFER_MODE_NONE = 0,
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XFER_MODE_PIO,
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XFER_MODE_DMA,
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};
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struct tegra_spi_channel {
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struct tegra_spi_regs *regs;
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/* static configuration */
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struct spi_slave slave;
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unsigned int req_sel;
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int dual_mode; /* for x2 transfers with bit interleaving */
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/* context (used internally) */
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u8 *in_buf, *out_buf;
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struct apb_dma_channel *dma_out, *dma_in;
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enum spi_xfer_mode xfer_mode;
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};
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struct cbfs_media;
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int initialize_tegra_spi_cbfs_media(struct cbfs_media *media,
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void *buffer_address,
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size_t buffer_size);
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struct tegra_spi_channel *tegra_spi_init(unsigned int bus);
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#endif /* __NVIDIA_TEGRA124_SPI_H__ */
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