coreboot-kgpe-d16/src
Aaron Durbin b3b1b5875c tegra132: increase MAX_CPUS to 2
There are 2 cores visible to the OS and both need to be
brought up. Therefore, provide the proper number of cores.

BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and noted CONFIG_MAX_CPUS=2.

Change-Id: I8a99891506af0fb3aa0284475c3c4be8bb69268b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: efa6c0343521dd98b86eacc94737f3497b721f95
Original-Change-Id: Id31b0a3046e40e1aec09bf2ee66b1e2f0b27fd21
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214661
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9006
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27 08:03:51 +01:00
..
arch arm64: clean up ramstage.ld 2015-03-27 08:03:50 +01:00
console console: Convert cbmem log line endings to UNIX standard 2015-03-25 17:25:14 +01:00
cpu cpu/amd/model_10xxx: Increase preram buffer size to 32k 2015-03-25 17:26:48 +01:00
device PCIe: Revise L1 Sub-State support 2015-03-23 13:11:18 +01:00
drivers vboot2: read secdata and nvdata 2015-03-23 19:51:47 +01:00
ec chromeec: Add ACPI device for PD MCU and handle related EC host event 2015-03-27 06:30:44 +01:00
include timer: remove rela_time type 2015-03-26 08:53:53 +01:00
lib cbfs: support concurrent media channels properly 2015-03-26 08:53:39 +01:00
mainboard ryu: normalize board id 2015-03-27 08:03:49 +01:00
northbridge cpu/amd/model_10xxx: Add support for early cbmem 2015-03-19 08:28:43 +01:00
soc tegra132: increase MAX_CPUS to 2 2015-03-27 08:03:51 +01:00
southbridge CBMEM: Add LATE_CBMEM_INIT guards 2015-03-19 06:17:07 +01:00
superio superio: ite8772f: Exit extemp busy state 2015-03-21 08:44:28 +01:00
vendorcode Chrome OS vendorcode: Fix vboot_reference compilation 2015-03-26 03:07:18 +01:00
Kconfig Enable publishing of board ID where supported 2015-03-23 17:20:24 +01:00