b439a92939
Fix the following warning detected by checkpatch: WARNING: line over 80 characters TEST=Build for glados Change-Id: I79341f46ca06ac052f987975ccaf975470d27806 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18867 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
460 lines
11 KiB
C
460 lines
11 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_CHIP_H_
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#define _SOC_CHIP_H_
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#include <arch/acpi_device.h>
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#include <device/i2c.h>
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#include <stdint.h>
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#include <soc/gpio_defs.h>
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#include <soc/gpe.h>
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#include <soc/irq.h>
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#include <soc/intel/common/lpss_i2c.h>
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#include <soc/pci_devs.h>
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#include <soc/pmc.h>
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#include <soc/serialio.h>
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#include <soc/usb.h>
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#include <soc/vr_config.h>
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#define SKYLAKE_I2C_DEV_MAX 6
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enum skylake_i2c_voltage {
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I2C_VOLTAGE_3V3,
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I2C_VOLTAGE_1V8
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};
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struct skylake_i2c_config {
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/* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
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enum i2c_speed speed;
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/* Bus should be enabled prior to ramstage with temporary base */
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int early_init;
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/* Custom bus speed configuration { scl_lcnt, scl_hcnt, sda_hold } */
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struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT];
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};
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struct soc_intel_skylake_config {
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/*
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* Interrupt Routing configuration
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* If bit7 is 1, the interrupt is disabled.
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*/
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uint8_t pirqa_routing;
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uint8_t pirqb_routing;
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uint8_t pirqc_routing;
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uint8_t pirqd_routing;
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uint8_t pirqe_routing;
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uint8_t pirqf_routing;
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uint8_t pirqg_routing;
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uint8_t pirqh_routing;
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/* GPE configuration */
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uint32_t gpe0_en_1; /* GPE0_EN_31_0 */
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uint32_t gpe0_en_2; /* GPE0_EN_63_32 */
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uint32_t gpe0_en_3; /* GPE0_EN_95_64 */
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uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */
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/* Gpio group routed to each dword of the GPE0 block. Values are
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* of the form GPP_[A:G] or GPD. */
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uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */
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uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */
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uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
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/* Generic IO decode ranges */
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen3_dec;
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uint32_t gen4_dec;
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/* Enable S0iX support */
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int s0ix_enable;
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/* Enable DPTF support */
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int dptf_enable;
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/* Deep SX enable for both AC and DC */
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int deep_s3_enable;
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int deep_s5_enable;
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/*
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* Deep Sx Configuration
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* DSX_EN_WAKE_PIN - Enable WAKE# pin
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* DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin
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* DSX_EN_AC_PRESENT_PIN - Enable AC_PRESENT pin
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*/
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uint32_t deep_sx_config;
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/* TCC activation offset */
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int tcc_offset;
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/*
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* The following fields come from FspUpdVpd.h.
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* These are configuration values that are passed to FSP during
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* MemoryInit.
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*/
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u64 PlatformMemorySize;
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u8 SmramMask;
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u8 MrcFastBoot;
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u32 TsegSize;
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u16 MmioSize;
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/*
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* DDR Frequency Limit
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* 0(Auto), 1067, 1333, 1600, 1867, 2133, 2400
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*/
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u16 DdrFreqLimit;
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/* Probeless Trace function */
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u8 ProbelessTrace;
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/*
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* System Agent dynamic frequency configuration
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* When enabled memory will be trained at two different frequencies.
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* 0 = Disabled
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* 1 = FixedLow
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* 2 = FixedHigh
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* 3 = Enabled
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*/
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u8 SaGv;
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/* Enable/disable Rank Margin Tool */
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u8 Rmt;
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/* Lan */
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u8 EnableLan;
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/* SATA related */
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u8 EnableSata;
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u8 SataMode;
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u8 SataSalpSupport;
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u8 SataPortsEnable[8];
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u8 SataPortsDevSlp[8];
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/* Audio related */
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u8 EnableAzalia;
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u8 DspEnable;
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/*
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* I/O Buffer Ownership:
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* 0: HD-A Link
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* 1 Shared, HD-A Link and I2S Port
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* 3: I2S Ports
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*/
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u8 IoBufferOwnership;
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/* Trace Hub function */
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u8 EnableTraceHub;
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/* Pcie Root Ports */
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u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
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u8 PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS];
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u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS];
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/* USB related */
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struct usb2_port_config usb2_ports[16];
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struct usb3_port_config usb3_ports[10];
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u8 XdciEnable;
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u8 SsicPortEnable;
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/* SMBus */
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u8 SmbusEnable;
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/*
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* SerialIO device mode selection:
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*
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* Device index:
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* PchSerialIoIndexI2C0
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* PchSerialIoIndexI2C1
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* PchSerialIoIndexI2C2
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* PchSerialIoIndexI2C3
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* PchSerialIoIndexI2C4
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* PchSerialIoIndexI2C5
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* PchSerialIoIndexI2C6
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* PchSerialIoIndexSpi0
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* PchSerialIoIndexSpi1
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* PchSerialIoIndexUart0
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* PchSerialIoIndexUart1
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* PchSerialIoIndexUart2
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*
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* Mode select:
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* PchSerialIoDisabled
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* PchSerialIoAcpi
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* PchSerialIoPci
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* PchSerialIoAcpiHidden
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* PchSerialIoLegacyUart
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*/
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u8 SerialIoDevMode[PchSerialIoIndexMax];
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/* I2C */
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/* Bus voltage level, default is 3.3V */
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enum skylake_i2c_voltage i2c_voltage[SKYLAKE_I2C_DEV_MAX];
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struct lpss_i2c_bus_config i2c[SKYLAKE_I2C_DEV_MAX];
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/* Camera */
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u8 Cio2Enable;
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u8 SaImguEnable;
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/* eMMC and SD */
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u8 ScsEmmcEnabled;
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u8 ScsEmmcHs400Enabled;
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u8 ScsSdCardEnabled;
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/* Integrated Sensor */
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u8 IshEnable;
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u8 PttSwitch;
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u8 HeciTimeouts;
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u8 HsioMessaging;
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u8 Heci3Enabled;
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/* Gfx related */
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u8 IgdDvmt50PreAlloc;
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u8 PrimaryDisplay;
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u8 InternalGfx;
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u8 ApertureSize;
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u8 SkipExtGfxScan;
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u8 ScanExtGfxForLegacyOpRom;
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/*
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* The following fields come from fsp_vpd.h
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* These are configuration values that are passed to FSP during
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* SiliconInit.
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*/
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u32 LogoPtr;
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u32 LogoSize;
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u32 GraphicsConfigPtr;
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u8 Device4Enable;
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u8 RtcLock;
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/* GPIO IRQ Route The valid values is 14 or 15*/
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u8 GpioIrqSelect;
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/* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/
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u8 SciIrqSelect;
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/* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23*/
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u8 TcoIrqSelect;
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u8 TcoIrqEnable;
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/* Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.*/
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u8 LockDownConfigGlobalSmi;
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/*
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* Enable BIOS Interface Lock Down bit to prevent writes to the Backup
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* Control Register. Top Swap bit and the General Control and Status
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* Registers Boot BIOS Straps.
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*/
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u8 LockDownConfigBiosInterface;
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/*
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* Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh
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* in the upper and and lower 128-byte bank of RTC RAM.
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*/
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u8 LockDownConfigRtcLock;
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/*
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* When enabled, the BIOS Region can only be modified from SMM after
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* EndOfDxe protocol is installed
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*/
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u8 LockDownConfigBiosLock;
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/*
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* Enable InSMM.STS (EISS) in SPI If this bit is set, then WPD must be a
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* '1' and InSMM.STS must be '1' also in order to write to BIOS regions
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* of SPI Flash. If this bit is clear, then the InSMM.STS is a don't
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* care. The BIOS must set the EISS bit while BIOS Guard support is
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* enabled.
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*/
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u8 LockDownConfigSpiEiss;
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/* Subsystem Vendor ID of the PCH devices*/
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u16 PchConfigSubSystemVendorId;
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/* Subsystem ID of the PCH devices*/
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u16 PchConfigSubSystemId;
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/*
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* Determine if WLAN wake from Sx, corresponds to the
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* HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
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*/
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u8 PchPmWoWlanEnable;
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/*
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* Determine if WLAN wake from DeepSx, corresponds to
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* the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register.
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*/
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u8 PchPmWoWlanDeepSxEnable;
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/*
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* Corresponds to the "WOL Enable Override" bit in the General PM
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* Configuration B (GEN_PMCON_B) register
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*/
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u8 WakeConfigWolEnableOverride;
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/* Determine if enable PCIe to wake from deep Sx*/
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u8 WakeConfigPcieWakeFromDeepSx;
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/* Deep Sx Policy. Values 0: PchDeepSxPolDisable,
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* 1: PchDpS5BatteryEn, 2: PchDpS5AlwaysEn, 3: PchDpS4S5BatteryEn,
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* 4: PchDpS4S5AlwaysEn, 5: PchDpS3S4S5BatteryEn, 6: PchDpS3S4S5AlwaysEn
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*/
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u8 PmConfigDeepSxPol;
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/*
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* SLP_S3 Minimum Assertion Width Policy. Values 0: PchSlpS360us,
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* 1: PchSlpS31ms, 2: PchSlpS350ms, 3: PchSlpS32s.
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*/
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u8 PmConfigSlpS3MinAssert;
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/*
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* SLP_S4 Minimum Assertion Width Policy. Values 0: PchSlpS4PchTime,
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* 1: PchSlpS41s, 2: PchSlpS42s, 3: PchSlpS43s, 4: PchSlpS44s.
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*/
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u8 PmConfigSlpS4MinAssert;
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/*
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* SLP_SUS Minimum Assertion Width Policy. Values 0: PchSlpSus0ms,
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* 1: PchSlpSus500ms, 2: PchSlpSus1s, 3: PchSlpSus4s.
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*/
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u8 PmConfigSlpSusMinAssert;
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/*
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* SLP_A Minimum Assertion Width Policy. Values 0: PchSlpA0ms,
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* 1: PchSlpA4s, 2: PchSlpA98ms, 3: PchSlpA2s.
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*/
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u8 PmConfigSlpAMinAssert;
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/*
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* This member describes whether or not the PCI ClockRun feature of PCH
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* should be enabled. Values 0: Disabled, 1: Enabled
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*/
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u8 PmConfigPciClockRun;
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/*
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* SLP_X Stretching After SUS Well Power Up. Values 0: Disabled,
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* 1: Enabled
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*/
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u8 PmConfigSlpStrchSusUp;
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/*
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* PCH power button override period.
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* Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s
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*/
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u8 PmConfigPwrBtnOverridePeriod;
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/*
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* PCH Pm Slp S0 Voltage Margining Enable
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* Indicates platform supports VCCPrim_Core Voltage Margining
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* in SLP_S0# asserted state.
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*/
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u8 PchPmSlpS0VmEnable;
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/*
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* Reset Power Cycle Duration could be customized in the unit of second.
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* PCH HW default is 4 seconds, and range is 1~4 seconds.
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* Values: 0x0 - 0s, 0x1 - 1s, 0x2 - 2s, 0x3 - 3s, 0x4 - 4s
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*/
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u8 PmConfigPwrCycDur;
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/* Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled.*/
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u8 SerialIrqConfigSirqEnable;
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/* Serial IRQ Mode Select. Values: 0: PchQuietMode,
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* 1: PchContinuousMode.
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*/
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u8 SerialIrqConfigSirqMode;
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/*
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* Start Frame Pulse Width.
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* Values: 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2; PchSfpw8Clk.
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*/
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u8 SerialIrqConfigStartFramePulse;
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u8 FspSkipMpInit;
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/*
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* VrConfig Settings for 5 domains
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* 0 = System Agent, 1 = IA Core, 2 = Ring,
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* 3 = GT unsliced, 4 = GT sliced
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*/
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struct vr_config domain_vr_config[NUM_VR_DOMAINS];
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/*
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* HeciEnabled decides the state of Heci1 at end of boot
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* Setting to 0 (default) disables Heci1 and hides the device from OS
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*/
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u8 HeciEnabled;
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/* PL2 Override value in Watts */
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u32 tdp_pl2_override;
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u8 PmTimerDisabled;
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/* Intel Speed Shift Technology */
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u8 speed_shift_enable;
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/*
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* Enable VR specific mailbox command
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* 000b - Don't Send any VR command
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* 001b - VR command specifically for the MPS IMPV8 VR will be sent
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* 010b - VR specific command sent for PS4 exit issue
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* 011b - VR specific command sent for both MPS IMPV8 & PS4 exit issue
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*/
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u8 SendVrMbxCmd;
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/* Enable/Disable VMX feature */
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u8 VmxEnable;
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/*
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* PRMRR size setting with three options
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* 0x02000000 - 32MiB
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* 0x04000000 - 64MiB
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* 0x08000000 - 128MiB
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*/
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u32 PrmrrSize;
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/* Statically clock gate 8254 PIT. */
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u8 clock_gate_8254;
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/*
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* Use SD card detect GPIO with default config:
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* - Edge triggered
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* - No internal pull
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* - Active both (high + low)
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* - Can wake device from D3
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* - 100ms debounce timeout
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*
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* GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 10000,
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* "\\_SB.PCI0.GPIO", 0, ResourceConsumer)
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* { sdcard_cd_gpio_default }
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*/
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unsigned int sdcard_cd_gpio_default;
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/* Use custom SD card detect GPIO configuration */
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struct acpi_gpio sdcard_cd_gpio;
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/* Wake Enable Bitmap for USB2 ports */
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u16 usb2_wake_enable_bitmap;
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/* Wake Enable Bitmap for USB3 ports */
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u8 usb3_wake_enable_bitmap;
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/*
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* Acoustic Noise Mitigation
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* 0b - Disable
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* 1b - Enable noise mitigation
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*/
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u8 AcousticNoiseMitigation;
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/*
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* Disable Fast Package C-state ramping
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* Need to set AcousticNoiseMitigation = '1' first
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* 0b - Enabled
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* 1b - Disabled
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*/
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u8 FastPkgCRampDisableIa;
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u8 FastPkgCRampDisableGt;
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u8 FastPkgCRampDisableSa;
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/*
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* Adjust the VR slew rates
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* Need to set AcousticNoiseMitigation = '1' first
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* 000b - Fast/2
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* 001b - Fast/4
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* 010b - Fast/8
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* 011b - Fast/16
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*/
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u8 SlowSlewRateForIa;
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u8 SlowSlewRateForGt;
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u8 SlowSlewRateForSa;
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};
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typedef struct soc_intel_skylake_config config_t;
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extern struct chip_operations soc_ops;
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#endif
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