b29078e401
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
122 lines
3.8 KiB
Text
122 lines
3.8 KiB
Text
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2007-2008 coresystems GmbH
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; version 2 of
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# the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# -----------------------------------------------------------------
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entries
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# -----------------------------------------------------------------
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# Status Register A
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# -----------------------------------------------------------------
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# Status Register B
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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388 4 h 0 reboot_counter
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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#392 3 r 0 unused
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395 4 e 6 debug_level
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#399 1 r 0 unused
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# coreboot config options: cpu
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400 1 e 2 hyper_threading
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#401 7 r 0 unused
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# coreboot config options: southbridge
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408 1 e 1 nmi
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#409 2 e 7 power_on_after_fail
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# coreboot config options: northbridge
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411 3 e 11 gfx_uma_size
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# coreboot config options: bootloader
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416 512 s 0 boot_devices
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928 8 h 0 boot_default
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936 1 e 8 cmos_defaults_loaded
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937 1 e 1 lpt
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#938 46 r 0 unused
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# coreboot config options: check sums
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984 16 h 0 check_sum
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#1000 24 r 0 amd_reserved
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# RAM initialization internal data
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1024 8 r 0 C0WL0REOST
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1032 8 r 0 C1WL0REOST
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1040 8 r 0 RCVENMT
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1048 4 r 0 C0DRT1
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1052 4 r 0 C1DRT1
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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6 1 Emergency
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6 2 Alert
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6 3 Critical
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6 4 Error
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6 5 Warning
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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8 0 No
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8 1 Yes
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9 0 Secondary
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9 1 Primary
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11 0 1M
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11 1 4M
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11 2 8M
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11 3 16M
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11 4 32M
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11 5 48M
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11 6 64M
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# -----------------------------------------------------------------
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checksums
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checksum 392 983 984
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