8cbf47f12c
Add device tree option to determine if the LPE
audio codec has a platform clock signal connected
to it from the SoC. If a frequency is selected the
platform clock number is used to enable the
clock.
BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted rambi with 25MHz option. Probed pin
to audio codec. Noted 25MHz clock.
Change-Id: I67d0d034f30ae1c7ee8269c0aea43e8c92ff868c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178780
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4986
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
90 lines
2.3 KiB
C
90 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <baytrail/iomap.h>
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#include <baytrail/pci_devs.h>
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#include <baytrail/pmc.h>
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#include <baytrail/ramstage.h>
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#include "chip.h"
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static void setup_codec_clock(device_t dev)
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{
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uint32_t reg;
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int clk_reg;
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struct soc_intel_baytrail_config *config;
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const char *freq_str;
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config = dev->chip_info;
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switch (config->lpe_codec_clk_freq) {
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case 19:
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freq_str = "19.2";
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reg = CLK_FREQ_19P2MHZ;
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break;
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case 25:
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freq_str = "25";
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reg = CLK_FREQ_25MHZ;
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break;
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default:
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printk(BIOS_DEBUG, "LPE codec clock not required.\n");
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return;
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}
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/* Default to always running. */
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reg |= CLK_CTL_ON;
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if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) {
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printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n");
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return;
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}
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printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
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clk_reg = PMC_BASE_ADDRESS + PLT_CLK_CTL_0;
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clk_reg += 4 * config->lpe_codec_clk_num;
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write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
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}
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static void lpe_init(device_t dev)
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{
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setup_codec_clock(dev);
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}
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static const struct device_operations device_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = NULL,
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.init = lpe_init,
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.enable = NULL,
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.scan_bus = NULL,
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.ops_pci = &soc_pci_ops,
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};
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static const struct pci_driver southcluster __pci_driver = {
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.ops = &device_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = LPE_DEVID,
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};
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