coreboot-kgpe-d16/src/soc/qualcomm/ipq806x/Kconfig
Vadim Bendebury b508a858b5 ipq806x: set architecture to ARMV7
BUG=chrome-os-partner:33646
BRANCH=ToT
TEST=Built storm.

Change-Id: I4b2cb54369dee7e6e61c2173d2be0f50430123fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0aab7fe31b78bae264cc2e6fa04fe7047315d08f
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Ic509e1fd375a320b8e37a07a7f5b9a6fa211ace3
Original-Reviewed-on: https://chromium-review.googlesource.com/229427
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9680
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15 21:55:19 +02:00

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config SOC_QC_IPQ806X
bool
default n
select ARCH_BOOTBLOCK_ARMV7
select ARCH_VERSTAGE_ARMV7
select ARCH_ROMSTAGE_ARMV7
select ARCH_RAMSTAGE_ARMV7
select ARM_LPAE
select BOOTBLOCK_CONSOLE
select DYNAMIC_CBMEM
select HAVE_UART_SPECIAL
select SPI_ATOMIC_SEQUENCING
if SOC_QC_IPQ806X
config CBFS_SIZE
hex "Size of CBFS filesystem in ROM"
default ROM_SIZE
help
CBFS size needs to match the size of memory allocated to the
coreboot blob elsewhere in the system. Make sure this config option
is fine tuned in the board config file.
config MBN_ENCAPSULATION
depends on USE_BLOBS
bool "bootblock encapsulation for ipq8064"
default y
config SBL_BLOB
depends on USE_BLOBS
string "file name of the Qualcomm SBL blob"
default "3rdparty/cpu/qualcomm/ipq806x/uber-sbl.mbn"
help
The path and filename of the binary blob containing
ipq806x early initialization code, as supplied by the
vendor.
endif