coreboot-kgpe-d16/src/soc/amd/stoneyridge/sata.c
Richard Spiegel c661c8eab1 soc/amd/stoneyridge: Improve code quality
Remove empty functions. In function pointer structure
"device_operations", replace the 0 equality by NULL equality.
Files: hda.c, sata.c and usb.c

Change-Id: I9f8dc7681ab2e651872e69a8b2e990e59ebe80c9
Signed-off-by: Richard Spiegel <richard.spiegel@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/21522
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15 19:28:11 +00:00

82 lines
2.3 KiB
C

/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <delay.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
#include <soc/southbridge.h>
static void sata_init(struct device *dev)
{
/**************************************
* Configure the SATA port multiplier *
**************************************/
#define BYTE_TO_DWORD_OFFSET(x) (x/4)
#define AHCI_BASE_ADDRESS_REG 0x24
#define MISC_CONTROL_REG 0x40
#define UNLOCK_BIT (1<<0)
#define SATA_CAPABILITIES_REG 0xfc
#define CFG_CAP_SPM (1<<12)
volatile u32 *ahci_ptr = (u32 *)(pci_read_config32(dev,
AHCI_BASE_ADDRESS_REG) & 0xffffff00);
u32 temp;
/* unlock the write-protect */
temp = pci_read_config32(dev, MISC_CONTROL_REG);
temp |= UNLOCK_BIT;
pci_write_config32(dev, MISC_CONTROL_REG, temp);
/* set the SATA AHCI mode to allow port expanders */
*(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG))
|= CFG_CAP_SPM;
/* lock the write-protect */
temp = pci_read_config32(dev, MISC_CONTROL_REG);
temp &= ~UNLOCK_BIT;
pci_write_config32(dev, MISC_CONTROL_REG, temp);
};
static struct pci_operations lops_pci = {
/* .set_subsystem = pci_dev_set_subsystem, */
};
static struct device_operations sata_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = sata_init,
.scan_bus = NULL,
.ops_pci = &lops_pci,
};
static const unsigned short pci_device_ids[] = {
PCI_DEVICE_ID_AMD_SB900_SATA,
PCI_DEVICE_ID_AMD_SB900_SATA_AHCI,
PCI_DEVICE_ID_AMD_CZ_SATA,
PCI_DEVICE_ID_AMD_CZ_SATA_AHCI,
0
};
static const struct pci_driver sata0_driver __pci_driver = {
.ops = &sata_ops,
.vendor = PCI_VENDOR_ID_AMD,
.devices = pci_device_ids,
};